Linearity and speed optimization in SOI LDMOS using gate engineering

This paper introduces a new SiGe Stepped Gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is successful in thick film devices, its effectiveness to thin film LDMOS is questionable, and also it imposes area penalty. Without a body contact, the floating body effects can be also reduced by decreasing the drift region doping [1]. But increased drift region resistance degrades the on-resistance of the device. The proposed device, SSG LDMOS circumvents the above challenges. It has a germanium implanted source and stepped field plate in the drift region. The SSG LDMOS reduces floating body effects in two ways. The SiGe source offers low potential to the excess holes generated due to the impact ionization [2]. The stepped gate reduces gate-drain capacitance improving the switching speed. The combined effect of (i) SiGe in the source and (ii) the stepped gate, improves the breakdown voltage and also allows us to increase the drift doping levels resulting in a reduced on-resistance. Using two dimensional device simulation [3], the proposed device is simulated and compared with the conventional thin film LDMOS. The cross-sectional view of both the devices is shown in Fig. 1. The conventional LDMOS has a uniform gate oxide thickness of 50 nm with a field plate. The drift region doping in both the devices is chosen for maximum breakdown voltage and is found to be 9×10 16 cm -3 (which is higher than the conventional device doping 3×10 16 cm -3 ). The germanium mole fraction in the SiGe source of the SSG LDMOS is chosen to be 0.2. The device parameters used in our simulation are given in Table 1. Figs. 2 and 3 show the breakdown characteristics and the on-resistance variation of the SSG LDMOS and the conventional LDMOS. The SSG LDMOS exhibits a 97% improvement in breakdown voltage and a 61% reduction in onresistance compared to the convetional LDMOS. Figs. 4 and 5 show the switching delay and the gate-charge behaviour. We observe that the SSG LDMOS exhibits a 57% reduction in switching delay and a 50% reduction in gate-drain charge compared to the conventional LDMOS. This work clearly demonstrates the application of SiGe source and a stepped oxide gate in improving the performance of the LDMOS making this device more useful in both RF and wireless system-onchip applications.

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

A new lateral double diffused metal oxide semiconductor (LDMOS) is proposed for the first time with the step oxide layer above the folding silicon substrate. Three technologies, including of the electric field modulation effect, majority carrier accumulation, and folding silicon, are applied simultaneously to the proposed LDMOS for improving the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The majority carrier accumulation layer under the extended gate is formed in the folding silicon substrate during the on-state operation. The high-doping drift region can be depleted completely in the off-state, thanks to an additional electric field modulation, which is analogous to the super junction idea. The uniform lateral electric field has been obtained due to the new electric field peak to improve the trade-off between the BV and R on,sp. The proposed LDMOS shows the R on,sp of 0.32 mΩ cm2 with the BV of 62 V, which has broken the silicon limit relationship with R on,sp of 2.0 mΩ cm2 under the same BV in the conventional LDMOS. This is the previously reported lowest R on,sp with the BV of about 60 V.

Optical diagnostics of plasma chemistries and chamber conditions in gate oxide stack etch

A novel lateral double-diffused metal—oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (Ron.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in Ron.sp by 45.7% simultaneously.

High voltage MOSFETs are widely used for bias ranges of a few dozens of volts to a few hundred of volts. The trench-type MOSFET is one of the key devices for realizing this wide range applications. However, the device characteristics are not yet well understood, especially, the Miller-capacitance variation for different device structures is still mysterious. Here we show, that the capacitance variation is very much dependent on the applied device structure. An observed capacitance increase as a function of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> , contrary to the conventional decreasing trend, is due to the large induced field within the highly resistive drift region. A narrow width of the drift region in a super-junction structure will easily become fully depleted, due to the junction between drift and pillar region of the substrate, which causes a fully depleted condition. This full-depletion situation induces a high field within the drift region, resulting in a potential increase even at the gate oxide.

A novel high-performance trench lateral double-diffused MOSFET with buried oxide bump layer

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

The breakdown characteristics of a practical silicon-on-insulator (SOI) lateral power device are generally limited by the 3-D curvature effect induced by its circular layout. The Conventional 2-D design methods such as 2-D variation of lateral doping (VLD) technique cannot derive optimal device parameters. In this paper, for the first time, a 3-D VLD technique is proposed to suppress the 3-D curvature effect in the lateral power device with circular layout. The 3-D Poisson equation is solved to formulate the optimized doping profile. TCAD tools are employed to verify the model and explore the physic insight. By adding an inversely proportional doping profile onto the conventional linear doping profile, the analytical and numerical results show that the uniform electric field in the drift region and maximized breakdown voltage (BV) are obtained for the SOI lateral double-diffused metal-oxide-semiconductor with circular layout. Furthermore, compared to the 2-D VLD device, the proposed 3-D VLD technique also contributes to excellent on-state characteristics, including the high on-state BV, reduced specific on-resistance, large saturation current, suppressed quasi-saturation effect, improved transconductance, and thus a large Baliga's figure of merits (BFOM).

Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation

A novel low ON-resistance strained lateral double-diffused MOSFET (LDMOS) with silicon-carbon (Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> ) source is proposed for low-voltage applications. Due to the lattice mismatch between silicon and Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> , the source-side Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> stressor introduces the lateral tensile stress and vertical compressive stress along the conduction path to enhance the electron mobility in the channel and drift regions and hence improves the ON-state characteristics. As the stress relaxation in the drift region, the strain-induced breakdown voltage (BV) deterioration can be neglected. The simulation results show that the ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) of the proposed device is decreased by 19.2% compared with the conventional LDMOS without strain at a gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 1 V. At the same time, the novel LDMOS achieves 47% and 28.8% increment in the drive current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,sat</sub> ) and peak transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,peak</sub> ), respectively, while keeping a nearly identical BV of 23.08 V. Besides, the improved cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and transconductance-to-current-ratio (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) are also obtained in the novel LDMOS.

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 /spl mu/m drift region), a specific on-resistance of 15.7 m/spl Omega/-cm/sup 2/ at room temperature, and a gate oxide field of 3 MV/cm.

Damage to thin gate oxides from etching of polysilicon gates was studied using gate oxide breakdown histograms and time-dependent dielectric breakdown measurements. The effect of various polysilicon etch parameters was investigated in a radio frequency (rf) triode etcher. Increasing rf power caused a substantial increase in damage. Reducing bias at constant power also resulted in an increase in damage, indicating that ion energy is not the only cause of damage. Area, isolation edge, and source/drain edge contributions to gate oxide defect densities were calculated as a function of rf power during polysilicon etch. As rf power was increased, the area contribution increased the most, indicating that gate oxide damage from polysilicon etching is not an edge phenomenon but a surface phenomenon. The effect of gate oxide thickness was investigated. Damage increased significantly as gate oxide thickness was reduced. Finally, the rf triode etcher was compared with a microwave electron cyclotron resonance (ECR) etcher. The ECR etcher caused fewer damaged capacitors, but some modifications to the triode etch process (such as lower rf power or pure chlorine chemistry) produced fewer damaged capacitors than the ECR.

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.