Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

This work provides a way to reduce the parasitic effect that is present in ordinary power MOSFETs. In this device, source and drain doping is eliminated from the design process using charge plasma technique leading to the reduction of parasitic effects due to parasitic bipolar junction transistor (BJT) from the device. A vertical metal oxide-semiconductor field effect transistor (VMOS) is proposed by employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor (VDMOS). In this work, the proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.

This paper analyzes the feasibility of using metal- oxide-semiconductor field-effect transistors (MOSFETs) operating in weak inversion as temperature sensors for on-chip thermal testing applications. MOSFETs in weak inversion are theoretically analyzed so as to know how their sensitivity to temperature depends on both dimensions and bias current. Theoretical predictions are then compared with simulations and experimental data resulting from MOSFETs fabricated in a commercial 0.35-μm CMOS technology. The MOSFETs are experimentally subjected to changes of temperature generated by either a heating chamber or an on-chip power dissipating device. The performance of MOSFETs in weak inversion is also compared with that in strong inversion and with that of parasitic bipolar junction transistors. In the context of on-chip thermal testing, MOSFETs in weak inversion offer advantages in terms of layout area, linearity, current consumption, and spread of the sensitivity to temperature due to process variations.

Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.

Two-dimensional (2-D) materials such as MoS2 and phosphorene provide an ideal platform to realize extremely thin body metal-oxide-semiconductor field effect transistors (MOSFETs) which is highly immune to short channel effects in the ultra-scaled regime. Even with the excellent electrostatic integrity inherent in 2-D system, however, 2-D materials suffer from the lack of efficient doping method which is crucial in MOSFETs technology. Recently, an unusual phase transition from semiconductor to metal driven by the thickness modulation has been predicted in mono-elemental 2-D material arsenene. Utilizing this extraordinary property, we propose doping-free arsenene heterostructure MOSFETs based on the lateral multilayer (metallic source)/monolayer (semiconducting channel)/multilayer (metallic drain) arsenene heterostructure. Metallic multilayer arsenene in the source and drain can serve as electrodes without doping. We investigate the potential performance of arsenene heterostructure MOSFETs through atomistic simulations using density functional theory and nonequilibrium Green’s function. The intrinsic upper limit of the on-state current in arsenene heterostructure MOSFETs is estimated by studying the effect of layer number in the source and drain. We comprehensively analyze the competitiveness of arsenene heterostructure MOSFETs through benchmarking with monolayer arsenene homostructure MOSFETs equipped with the highly degenerate doped source and drain, suggesting superior performance of heterostructure MOSFETs over homostructure MOSFETs.

Electrical characterization and carrier transportation in Hf-silicate dielectrics using ALD gate stacks for 90 nm node MOSFETs

Any applications would prefer to have the circuits which are of high speed and consumes less power. To meet these requirements, the scaling of the circuits which are generally designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is done. Too much scaling down of the transistors or the integrated circuits (IC) affects the channel of the transistors causing Short Channel Effects (SCEs) which in turn affecting the reliability and performance of the circuits. To avoid this issue, a substitute of MOSFET known as Fin Field Effect Transistors (FinFE T) is used in the circuits. This helps to reduce the scaling needed and also has the better performance than the MOSFETs. This work demonstrates the advantageous performance of the FinFE Ts by implementing some of the basic building blocks of the digital circuits such as Inverter, NAND gate, NOR gate, a combinational circuit like Full Adder and a sequential circuit like SR Flip Flop. The designs are simulated using HSPICE tool at 45 nm technology. The parameters such as static power dissipation, dynamic power dissipation, rise time and fall time are examined through waveforms. The circuits with MOSFETs have the higher values from the parameters than the circuits with FinFETs.

Since the introduction of silicon-based thyristors in 1957, researchers in the field of power semiconductor devices have achieved remarkable progress. In the late 1960s, the gate turn-off thyristor (GTO) made it possible to turn off the latching thyristor devices using their gate terminals, enabling switching frequencies exceeding 1 kHz. In the mid-1970s, new silicon bipolar junction transistors and metal-oxide-semiconductor field-effect transistors (MOSFET) were introduced, pushing switching frequencies upward above 10 kHz. The insulated-gate bipolar transistor (IGBT) was developed in the 1980s with combined features of the MOSFET and bipolar transistor that made it an appealing choice for many power electronics applications, including motor drives. Today, IGBTs are the dominant power switching devices for power electronic converters operating at voltages greater than 600 Vdc.

With the development of down-scaling of CMOS technology for low power, mixed-signal, and high frequency applications, the optimal high frequency performance is shown to be shifted from lower moderate inversion toward weak inversion regimes. High-frequency noise model is a prerequisite for designing the radio frequency and millimeter-wave circuits, and is essential for the noise analysis of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, based on the physical structure of 40 nm MOSFET and by considering the drift-diffusion equation and charge conservation law, accurate physics-based unified high-frequency noise model is developed for induced gatecurrent noise and its cross-correlation with drain-current noise under different bias conditions, which is used to describe the frequency and bias dependence of 40 nm MOSFET from weak inversion to strong inversion regime. Especially, the effective gate overdrive is explicitly included in unified noise model to offer excellent accuracy, continuity and smoothness, and this makes the proposed analytical models convenient to directly reflect the relationship between the noise model and bias condition. Besides, new analytical model is derived for the induced-gate current noise and its cross-correlation term of weakly inverted MOSFET. These simple expressions not only serve as the asymptotic limit for the validation of the proposed physics-based unified model, but also provide a clearer insight into and better understanding of the gate noise behavior and their cross-correlation in the weak-inversion region. Moreover, in terms of the proposed subthreshold noise model, the charge of weak inversion rather than the normal effective channel thickness approximation is involved. In this way, the model accuracy can be improved. Furthermore, a detailed derivation and discussion are presented by analyzing the physics-based noise generation mechanism of transistor including the channel thermal noise and the shot noise based on the small-signal equivalent circuit of the 40 nm MOSFET device. Using these expressions it is possible to extract the values of all the noise model parameters directly from measurement. The proposed model is demonstrated by using noise data from both measurement and the noise simulation. Excellent agreement between simulated and measured noise data shows that the proposed model can be used for predicting the noise behavior of 40 nm MOSFET under different dimensions and operating conditions. The applicability of reported model for drain-current noise is also verified. As far as small-signal (i.e., linear) bias-dependent operation is concerned, it is shown how most of the findings of this work can also be used to predict the data of long channel devices in the strong-inversion regimes.

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

The precision of radiation therapy treatment depends on several calibration and quality assurance processes. In-vivo dosimetry (IVD) is used in external beam radiotherapy to evaluate the delivered versus planned dose as a patient-specific quality assurance verification procedure. This study aimed at assessing the performance of diodes (EDP-103G and EDP-203G) and metal oxide semiconductor field-effect transistors (MOSFETs) and corresponding correction factors followed by IVD evaluation in different treatment configurations. Linearity, stability, gantry angle, field size, and source-to-subject distance (SSD) were assessed across various photon energies, with correction factors determined. To minimize patient movement uncertainty, the study utilized the Alderson Rando phantom to replicate clinical setups, comparing diode and MOSFET dose readings to treatment planning system (TPS) doses. Diodes and MOSFETs were evaluated across different photon energy levels for brain, chest, and pelvis planning sites. Diodes and MOSFETs demonstrated good stability and linearity at the different utilized photon beams. Data analysis showed that MOSFETs had a slightly higher sensitivity compared to diodes in gantry angle, field size and SSD corrections. Regarding the validation process after applying the correction factors, dose variations between diode readings and TPS doses were found to be 1.89%, 1.58%, and 6.72% for brain, breast, and pelvis, respectively. In contrast, MOSFET readings were 2.40% for brain, 2.03% for chest, and 2.03% for pelvis. It is concluded that, while diode and MOSFET dosimeters both allowed for accurate patient dose measurements, for different anatomical sites, MOSFETs demonstrated better performance for the pelvis compared to diodes.

The purpose of this work was to estimate skin dose for the patients treated with Tomotherapy using metal oxide semiconductor field-effect transistors (MOSFETs) and thermoluminescent dosimeters (TLDs). In vivo measurements were performed for two head and neck patients treated with tomotherapy and compared to TLD measurements. The measurements were subsequently carried out for five days to estimate the inter-fraction deviations in MOSFET measurements. The variation between skin dose measured with MOSFET and TLD for first patient was 2.2%. Similarly, the variation of 2.3% was observed between skin dose measured with MOSFET and TLD for second patient. The Tomotherapy treatment planning system overestimated the skin dose as much as by 10-12% when compared to both MOSFET and TLD. However, the MOSFET measured patient skin doses also had good reproducibility, with inter-fraction deviations ranging from 1% to 1.4%. MOSFETs may be used as a viable dosimeter for measuring skin dose in areas where the treatment planning system may not be accurate.

This paper investigates the performance of faulty discrete metal-oxide-semiconductor field-effect transistors (MOS-FETs) in fault-tolerant high step-up dc-dc converters. This study targets low-power applications where both silicon (Si) and silicon carbide (SiC) technologies could be used at the low- and high-voltage sides, respectively. First, random samples of defective MOSFETs (i.e. for both technologies) were collected from testing real prototypes in the field. The statistics show that Si MOSFETs have 100% short-circuit fault (SCF) as the failure mode, while SiC MOSFETs have 82% SCF probability and 18% open-circuit fault probability. The ohmic resistance of a shorted MOSFET is measured using the impedance analyzer of Keysight E4990A to characterize the behavior of the switches after a fault Various combinations of short-circuited MOSFETs with different drain-source resistances were used in a real prototype, and the efficiency of the converter was evaluated in each case. The results prove the feasibility of using the short-circuited faulty MOSFET as a conduction path to overcome a SCF.

Previous research on flyback power factor correction (PFC) converters exposes some inherent shortcomings, such as high‐voltage spike on the metal oxide semiconductor field effect transistor (MOSFET), frequency variation, pulsating input current and hard switching operation. This study presents a new topology for PFC applications named zero‐voltage switching (ZVS) current‐fed flyback converter to not only achieve spike‐free voltage, ZVS on the MOSFETs, but also improve the input current quality. By utilising quasi‐z‐source configuration, the voltage spikes on the MOSFET are effectively eliminated using only a capacitive clamper, resulting in no‐loss consumption. Low‐voltage MOSFETs with low on‐resistance Rds(on) are used to improve the efficiency. In addition, by taking advantage of the average current mode control with the continuous conduction mode operation, the input current perfectly tracks the input voltage. To demonstrate the circuit's feasibility, a 100–140 V input, 28 V/5 A output laboratory prototype was built. The experimental results showed that the proposed topology completely eliminated the voltage spikes on the MOSFETs. The efficiency was improved using low Rds(on) MOSFETs, and ZVS was achieved. In summary, the proposed topology meets the high efficiency and high‐input current quality requirements.

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.