Enhanced VDMOS design with reduced parasitic effect

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

The groundbreaking demonstration of the first single-crystal gallium oxide (Ga2O3) transistors in 2011 galvanized intensive international research activities into the science and engineering of this new oxide semiconductor [1]. Much of the research and development has been motivated and inspired by the unique material properties of Ga2O3 based on an extremely large bandgap of 4.5 eV and the availability of large-size, high-quality, affordable single-crystal wafers produced from melt-grown bulk crystals. For the past several years, world-wide efforts on the development of Ga2O3 transistors have mostly been devoted to lateral field-effect transistors (FETs). However, as is well known, a vertical device geometry is much more suitable for high-voltage and/or high-current applications than a lateral geometry, because the former allows for high current drives without having to enlarge the device chip size, simplified thermal management, and far superior field termination. In this talk, we will present our state-of-the-art vertical Ga2O3 FET technologies. We fabricated depletion-mode vertical Ga2O3 metal-oxide-semiconductor FETs (MOSFETs) with a current aperture formed by buried current blocking layers (CBLs) [2]. The devices were fabricated on a 5-µm-thick n-Ga2O3 drift layer with a Si doping density of 2.5×1016 cm-3 grown by halide vapor phase epitaxy (HVPE) on an n +-Ga2O3 (001) substrate [3]. Three ion implantation process steps were employed to form Si-doped n +-regions (Si=5×1019 cm-3, 0.1-µm-thick box profile) for the source ohmic contacts, a Si-doped n-channel (Si=1.5×1018 cm-3, 0.15-µm-thick box profile), and nitrogen (N)-doped p-type CBLs in the HVPE drift layer. N was ion-implanted at an energy of 480 keV and a dose of 4×1013 cm-2, followed by thermal annealing at 1100°C for activation. Note that we found that N atoms doped in Ga2O3 act as deep acceptors to compensate background electrons, and that our development of the N-ion implantation doping process was a technological breakthrough [4], which would lead to the fabrication of planar-gate vertical MOSFETs. The current aperture vertical MOSFET showed decent device characteristics such as a maximum drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and a high drain current on/off ratio of over eight orders of magnitude. The off-state breakdown voltage was limited to less than 30 V owing to the large electric field in the Al2O3 gate dielectric, but can be increased by improving material quality of the gate dielectric and optimizing doping schemes. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: New Energy and Industrial Technology Development Organization). [1] M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 100, 103504 (2012). [2] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, in press (2019). [3] K. Goto, K. Konishi, H. Murakami, Y. Kumagai, B. Monemar, M. Higashiwaki, A. Kuramata, and S. Yamakoshi, Thin Solid Films 666, 182 (2018). [4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

A vertical metal oxide semiconductor field-effect transistor (VMOST) incorporating a dielectric pocket (DP) with epitaxial growth has been presented using two-dimensional simulation tools. A comparison between the non-DP VMOST and DP-VMOST was performed. It was shown that DP-VMOST had a better output than non-DP VMOST. The DP-VMOST with a body doping concentration of 2 ×1018 cm-3 and a spacing between the pocket and the gate oxide, WC, of 5 nm resulted in a threshold voltage of 0.35 V, an off-state leakage current of 1.31 ×10-8 A/µm, a subthreshold slope of 76.2 mV, and a drain current of 1069.77 µA/µm. For non-DP VMOST, the results showed a lower threshold voltage and a higher off-state leakage current. The dielectric pocket allowed the suppression of short-channel effects and punchthrough drain to the body. A comparison of the simulation results with experimental results by other researchers has also been performed with ISE simulation software.

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state (<TEX>$5{\times}10^{17}cm^{-3}$</TEX>). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from <TEX>$1{\times}10^{16}cm^{-3}$</TEX> to <TEX>$1{\times}10^{17}cm^{-3}$</TEX>, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

We propose a hybrid self-curing method based on the parasitic bipolar junction transistor (PBJT) inherent to metal-oxide-semiconductor field-effect transistor (MOSFET). The PBJT utilizes the positive feedback of impact ionization to flow a large current close to the channel, generating Joule heat. Unlike conventional self-curing methods, the PBJT-based self-curing recovers the damaged gate oxide along the lateral dimension of the entire channel. The effects of the hybrid curing are quantitatively verified by low-frequency noise spectroscopy and charge pumping method.

This paper analyzes the feasibility of using metal- oxide-semiconductor field-effect transistors (MOSFETs) operating in weak inversion as temperature sensors for on-chip thermal testing applications. MOSFETs in weak inversion are theoretically analyzed so as to know how their sensitivity to temperature depends on both dimensions and bias current. Theoretical predictions are then compared with simulations and experimental data resulting from MOSFETs fabricated in a commercial 0.35-μm CMOS technology. The MOSFETs are experimentally subjected to changes of temperature generated by either a heating chamber or an on-chip power dissipating device. The performance of MOSFETs in weak inversion is also compared with that in strong inversion and with that of parasitic bipolar junction transistors. In the context of on-chip thermal testing, MOSFETs in weak inversion offer advantages in terms of layout area, linearity, current consumption, and spread of the sensitivity to temperature due to process variations.

Silica films on silicon carbide: a review of electrical properties and device applications

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (RDS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in RDS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in RDS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs.

Negative bias temperature instabilities (NBTI) are commonly observed in p-channel metal-oxide-semiconductor (MOS) devices when exposed to negative gate voltages at elevated temperatures. We present a brief overview of NBT stress- induced threshold voltage instabilities in p-channel vertical double-diffused MOS field-effect transistors (VDMOSFETs). NBT stress-induced threshold voltage shifts are fitted using different models to estimate the device lifetime and to discuss the impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection. The stretched exponential equation is found to provide excellent fit to experimental data for the later stress phases and thus allows an accurate estimation of device lifetime for the lowest stress voltage applied, which justifies the use of this or some other suitable fitting equation. The realistic failure criterion for devices and experimental conditions used in our studies is found to fall in the 100 - 150 mV range. The lifetime estimates are found to strongly depend on the model used for extrapolation to normal operating conditions. The 1/V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> model is shown to provide much faster output since it appears to allow the use of higher stress voltages while still yielding rather accurate lifetime estimates. Intermittent annealing does not seem to have any significant impact on device lifetime.

In this letter, monolithic integration of InGaN/GaN light emitting diodes (LEDs) with vertical metal-oxide-semiconductor field effect transistor (VMOSFET) drivers have been proposed and demonstrated. The VMOSFET was achieved by simply regrowing a p- and n-GaN bilayer on top of a standard LED structure. After fabrication, the VMOSFET is connected with the LED through the conductive n-GaN layer, with no need of extra metal interconnections. The junction-based VMOSFET is inherently an enhancement-mode (E-mode) device with a threshold voltage of 1.6 V. By controlling the gate bias of the VMOSFET, the light intensity emitted from the integrated VMOSFET-LED device could be well modulated, which shows great potential for various applications, including solid-state lighting, micro-displays, and visible light communications.

Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.

A major challenge in scaling metal-oxide-semiconductor field-effect transistors (MOSFETs) is controlling the gate length, L/sub G/. Variable L/sub G/ leads to variable current drive, requiring conservative digital designs, and to device mismatch that makes the fastest transistors unusable in precision analog designs. The vertical, replacement-gate (VRG) process uses the thickness of a deposited film to precisely define the gate length, while preserving the small gate overlap capacitances and shallow, self-aligned source/drain extensions that are critical to modern MOSFETs. In brief, a silicon device pillar is grown through a multilayer sandwich, whose center layer is later removed and replaced by the gate, and whose upper and lower layers provide dopants for the source/drain extensions. The gate dielectric can be thin, high-quality, thermal SiO/sub 2/ grown on [100]-oriented single-crystal silicon. Previous vertical MOSFET schemes inherently result in poor gate length control, high gate overlap capacitances, or low-quality gate oxides. The first VRG-MOSFETs are competitive with optimized short-channel planar MOSFETs. L/sub G/=200 nm (L/sub ch//spl Gt/190 nm) VRG-n MOSFETs have I/sub on/=1.1 mA//spl mu/m with I/sub off/=11 pA//spl mu/m (and subthreshold swing s=76 mV/dec).

Any applications would prefer to have the circuits which are of high speed and consumes less power. To meet these requirements, the scaling of the circuits which are generally designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is done. Too much scaling down of the transistors or the integrated circuits (IC) affects the channel of the transistors causing Short Channel Effects (SCEs) which in turn affecting the reliability and performance of the circuits. To avoid this issue, a substitute of MOSFET known as Fin Field Effect Transistors (FinFE T) is used in the circuits. This helps to reduce the scaling needed and also has the better performance than the MOSFETs. This work demonstrates the advantageous performance of the FinFE Ts by implementing some of the basic building blocks of the digital circuits such as Inverter, NAND gate, NOR gate, a combinational circuit like Full Adder and a sequential circuit like SR Flip Flop. The designs are simulated using HSPICE tool at 45 nm technology. The parameters such as static power dissipation, dynamic power dissipation, rise time and fall time are examined through waveforms. The circuits with MOSFETs have the higher values from the parameters than the circuits with FinFETs.