The vertical replacement-gate (VRG) process for scalable general-purpose complementary logic

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

A two-dimensional analytical model of a metal-oxide-semiconductor field-effect transistor (MOSFET) has been developed to examine theoretically the effect of ionizing radiation on the characteristics of an ion-implanted MOSFET. The radiation-induced change in the flat-band voltage have been utilized to estimate the characteristics of the device in the post-irradiated condition. The model has been used in conjunction with the Level-2 models of the SPICE package for estimating the I D – V D characteristics of the MOSFET in the post-irradiated condition. The model has been validated by reported experimental results. The two-dimensional nature of the model enables it to characterize even short-channel MOSFETs in the pre- and post-irradiated conditions.

A numerical analysis of avalanche breakdown in short-channel MOSFETs

An in-depth study on WENO-based techniques to improve parameter extraction procedures in MOSFET transistors

Lanthanum aluminate (LaAlO3) is considered as a potential candidate for high-K dielectric applications. LaAlO3 has high dielectric constant (13-27), large energy band gap (over 5eV), high thermal stability (up to 850°C), low leakage current density, large electron band offset. The structure of Al/LaAlO3/Si capacitors and transistors were fabricated successfully. The oxide films were deposited by rf-sputtering. The leakage current density was 4.36×10-3A/cm2 when the applied voltage was -1V. The measured dielectric constant was 13.4. The dominant electrical conduction mechanism of LaAlO3 thin film was Schottky emission mechanism at 450K. The electron barrier-height between Al/LaAlO3 interface and electron effective mass in the LaAlO3 film were about 0.94 eV and 0.07 m0, respectively. Secondary ion mass spectrometry (SIMS) and X-ray diffraction (XRD) were also used to examine the material properties of LaAlO3. The electrical characteristics of N-channel metal-oxide-semiconductor field effect transistors were also measured. The interface trapped charge density, effective electron mobility and sub-threshold swing were 2.27x1012cm-2-eV, 210cm2/V-s and 82.8 mV/dec., respectively. The degradation mechanisms of effective electron channel mobility and the threshold voltage shift in LaAlO3-gated n-MOSFETs were studied by analyzing experimental data at various temperatures from 11 K to 450 K. The mechanisms that influence the electron mobility include coulomb scattering, phonon scattering, surface roughness scattering.

A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as $\rm SiO_2$, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness ($\rm T_{OX}$) for each gate stack, including $\rm SiO_2$ interface layer and one high-k material. For the same EOT, $\rm Al_2O_3$ (k=9) over 3 $\rm\AA$ $\rm SiO_2$ provides the best performance, while for $\rm HfO_2$ (k=20) and $\rm La_2O_3$ (k=30), $\rm SiO_2$ thicknesses should be 5 $\rm\AA$ and 7 $\rm\AA$, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

The precision of radiation therapy treatment depends on several calibration and quality assurance processes. In-vivo dosimetry (IVD) is used in external beam radiotherapy to evaluate the delivered versus planned dose as a patient-specific quality assurance verification procedure. This study aimed at assessing the performance of diodes (EDP-103G and EDP-203G) and metal oxide semiconductor field-effect transistors (MOSFETs) and corresponding correction factors followed by IVD evaluation in different treatment configurations. Linearity, stability, gantry angle, field size, and source-to-subject distance (SSD) were assessed across various photon energies, with correction factors determined. To minimize patient movement uncertainty, the study utilized the Alderson Rando phantom to replicate clinical setups, comparing diode and MOSFET dose readings to treatment planning system (TPS) doses. Diodes and MOSFETs were evaluated across different photon energy levels for brain, chest, and pelvis planning sites. Diodes and MOSFETs demonstrated good stability and linearity at the different utilized photon beams. Data analysis showed that MOSFETs had a slightly higher sensitivity compared to diodes in gantry angle, field size and SSD corrections. Regarding the validation process after applying the correction factors, dose variations between diode readings and TPS doses were found to be 1.89%, 1.58%, and 6.72% for brain, breast, and pelvis, respectively. In contrast, MOSFET readings were 2.40% for brain, 2.03% for chest, and 2.03% for pelvis. It is concluded that, while diode and MOSFET dosimeters both allowed for accurate patient dose measurements, for different anatomical sites, MOSFETs demonstrated better performance for the pelvis compared to diodes.

The purpose of this work was to estimate skin dose for the patients treated with Tomotherapy using metal oxide semiconductor field-effect transistors (MOSFETs) and thermoluminescent dosimeters (TLDs). In vivo measurements were performed for two head and neck patients treated with tomotherapy and compared to TLD measurements. The measurements were subsequently carried out for five days to estimate the inter-fraction deviations in MOSFET measurements. The variation between skin dose measured with MOSFET and TLD for first patient was 2.2%. Similarly, the variation of 2.3% was observed between skin dose measured with MOSFET and TLD for second patient. The Tomotherapy treatment planning system overestimated the skin dose as much as by 10-12% when compared to both MOSFET and TLD. However, the MOSFET measured patient skin doses also had good reproducibility, with inter-fraction deviations ranging from 1% to 1.4%. MOSFETs may be used as a viable dosimeter for measuring skin dose in areas where the treatment planning system may not be accurate.

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of

Effective work function is the one of main parameters to determine threshold voltage in high-k metal gate (HKMG) metal-oxide-semiconductor field-effect transistor (MOSFET). This paper reported the relationships between the effective metal work function and gate length in HKMG MOSFET for the first time. The decrease of gate length induces an increment of metal gate's effective work function, which is caused by fact that the filling thickness of the work function metal layer in gate stack becomes thinner with the decrease of gate length. Thus, there is less Al migrates to metal/high-k interface to form dipoles.

Any applications would prefer to have the circuits which are of high speed and consumes less power. To meet these requirements, the scaling of the circuits which are generally designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is done. Too much scaling down of the transistors or the integrated circuits (IC) affects the channel of the transistors causing Short Channel Effects (SCEs) which in turn affecting the reliability and performance of the circuits. To avoid this issue, a substitute of MOSFET known as Fin Field Effect Transistors (FinFE T) is used in the circuits. This helps to reduce the scaling needed and also has the better performance than the MOSFETs. This work demonstrates the advantageous performance of the FinFE Ts by implementing some of the basic building blocks of the digital circuits such as Inverter, NAND gate, NOR gate, a combinational circuit like Full Adder and a sequential circuit like SR Flip Flop. The designs are simulated using HSPICE tool at 45 nm technology. The parameters such as static power dissipation, dynamic power dissipation, rise time and fall time are examined through waveforms. The circuits with MOSFETs have the higher values from the parameters than the circuits with FinFETs.

This work provides a way to reduce the parasitic effect that is present in ordinary power MOSFETs. In this device, source and drain doping is eliminated from the design process using charge plasma technique leading to the reduction of parasitic effects due to parasitic bipolar junction transistor (BJT) from the device. A vertical metal oxide-semiconductor field effect transistor (VMOS) is proposed by employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor (VDMOS). In this work, the proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.

The effects of electron–electron scattering on the electron energy distribution, as well as substrate and gate currents in short channel MOSFETs (metal-oxide-semiconductor field-effect transistors) are explored using the convective scheme, or CS, a method of characteristics. Effects of electron–electron scattering are explored for a MOSFET with uniform doping in the channel as well as for an asymmetric device structure, a focused-ion-beam (FIBMOS) transistor, for both 70 nm and 250 nm channel length devices. Effects of electron–electron scattering on a standard 35 nm channel length MOSFET are also included. The high substrate doping that is required for such short channel length devices leads to large electric fields. The purpose of the FIB implant is to improve hot-carrier reliability by reducing the electric field in the channel. Electron–electron scattering increases the amount of electrons in the tail, despite the fact that the applied potential is significantly below the threshold for injection of electrons into the gate oxide. The ratio of gate-to-substrate current, Ig/Isub, is investigated as an indicator of the level of degradation. At such short channel lengths, there are degrading and non-degrading components of gate and substrate current. The non-degrading components of gate and substrate current correlate strongly, so that the ratio of Ig/Isub is an efficient indicator of device degradation. The energy thresholds for impact ionization and for emission of electrons into the gate oxide are crucial in determining the ratio of these currents. The substrate and gate currents obtained indicate that hot-carrier effects continue to be an issue for device performance, even for nanometer-scale devices. The density of electrons is higher at very short channel lengths due to the need to have shallow junctions and leads to a greater amount of Coulomb collisions. Increased Coulomb collisions may lead to strongly reduced lifetimes in nanometer-scale devices.

Previous research on flyback power factor correction (PFC) converters exposes some inherent shortcomings, such as high‐voltage spike on the metal oxide semiconductor field effect transistor (MOSFET), frequency variation, pulsating input current and hard switching operation. This study presents a new topology for PFC applications named zero‐voltage switching (ZVS) current‐fed flyback converter to not only achieve spike‐free voltage, ZVS on the MOSFETs, but also improve the input current quality. By utilising quasi‐z‐source configuration, the voltage spikes on the MOSFET are effectively eliminated using only a capacitive clamper, resulting in no‐loss consumption. Low‐voltage MOSFETs with low on‐resistance Rds(on) are used to improve the efficiency. In addition, by taking advantage of the average current mode control with the continuous conduction mode operation, the input current perfectly tracks the input voltage. To demonstrate the circuit's feasibility, a 100–140 V input, 28 V/5 A output laboratory prototype was built. The experimental results showed that the proposed topology completely eliminated the voltage spikes on the MOSFETs. The efficiency was improved using low Rds(on) MOSFETs, and ZVS was achieved. In summary, the proposed topology meets the high efficiency and high‐input current quality requirements.

With the development of down-scaling of CMOS technology for low power, mixed-signal, and high frequency applications, the optimal high frequency performance is shown to be shifted from lower moderate inversion toward weak inversion regimes. High-frequency noise model is a prerequisite for designing the radio frequency and millimeter-wave circuits, and is essential for the noise analysis of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, based on the physical structure of 40 nm MOSFET and by considering the drift-diffusion equation and charge conservation law, accurate physics-based unified high-frequency noise model is developed for induced gatecurrent noise and its cross-correlation with drain-current noise under different bias conditions, which is used to describe the frequency and bias dependence of 40 nm MOSFET from weak inversion to strong inversion regime. Especially, the effective gate overdrive is explicitly included in unified noise model to offer excellent accuracy, continuity and smoothness, and this makes the proposed analytical models convenient to directly reflect the relationship between the noise model and bias condition. Besides, new analytical model is derived for the induced-gate current noise and its cross-correlation term of weakly inverted MOSFET. These simple expressions not only serve as the asymptotic limit for the validation of the proposed physics-based unified model, but also provide a clearer insight into and better understanding of the gate noise behavior and their cross-correlation in the weak-inversion region. Moreover, in terms of the proposed subthreshold noise model, the charge of weak inversion rather than the normal effective channel thickness approximation is involved. In this way, the model accuracy can be improved. Furthermore, a detailed derivation and discussion are presented by analyzing the physics-based noise generation mechanism of transistor including the channel thermal noise and the shot noise based on the small-signal equivalent circuit of the 40 nm MOSFET device. Using these expressions it is possible to extract the values of all the noise model parameters directly from measurement. The proposed model is demonstrated by using noise data from both measurement and the noise simulation. Excellent agreement between simulated and measured noise data shows that the proposed model can be used for predicting the noise behavior of 40 nm MOSFET under different dimensions and operating conditions. The applicability of reported model for drain-current noise is also verified. As far as small-signal (i.e., linear) bias-dependent operation is concerned, it is shown how most of the findings of this work can also be used to predict the data of long channel devices in the strong-inversion regimes.