Highly parallel pulsed optoelectronic analog-digital converter

The static maximum relative error of the ADC for sensors is determined by the value of its least significant bit. During the input signal conversion in the ADC the information delay causes the dynamic error, which is added to the static error and actually reduces the effective number of bits. This decrease can be estimated by the effective number of bits, which illustrates the qualitative and quantitative assessment of the additional error. The article demonstrates that the effective bits rate is defined by the delay period of information in the ADC, as well as the sampling rate of the input signal. This, in turn, requires setting the spectrographic density (SD) for the converted signal, as well as an algorithm for selecting the sampling rate. It is recommended that the delay time of the ADC includes the delay in the analog storage and amplitude multiplexer, which are located at the ADC input and are directly involved in the conversion process. The article draws attention to the fact that the real sampling rate of analog signals, chosen from the point of view of the straight task of errors distribution in the automatic control system, significantly exceeds the sampling rate according to the sampling theorem. This requires the correction of the obtained results using the sampling theorem, in the direction of reduction of effective number of bits.

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.

Solar radio spectra and their temporal evolution provide important clues to understand the energy release and electron acceleration process in the corona, and are commonly used to diagnose critical parameters such as the magnetic field strength. However, previous solar radio telescopes cannot provide high-quality data with complete frequency coverage. Aiming to develop a generalized solar radio observing system, in this study, we designed a digital receiving system that could capture solar radio bursts with a broad bandwidth and a large dynamic range. A dual-channel analog-to-digital converter (ADC) printed circuit board assembly (PCBA) with a sampling rate of 14-bit, 1.25 Giga samples per second (GSPS) cooperates with the field-programmable-gate-array (FPGA) chip XC7K410T in the design. This receiver could realize the real-time acquisition and preprocessing of high-speed data of up to 5 GB s−1, which ensures high time and spectral resolutions in observations. This receiver has been used in the solar radio spectrometer working in the frequency range of 35 to 40 GHz in Chashan Solar Observatory (CSO) established by Shandong University, and will be further developed and used in the solar radio interferometers. The full-power bandwidth of the PCBA in this receiving system could reach up to 1.5 GHz, and the performance parameters (DC–1.5 GHz) are obtained as follows: spur free dynamic range (SFDR) of 64.7–78.4 dB, signal-to-noise and distortion (SINAD) of 49.1–57.2 dB, and effective number of bits (ENOB) of > 7.86 bit. Based on the receiver that we designed, real-time solar microwave dynamic spectra have been acquired and more solar microwave bursts with fine spectral structures are hopeful to be detected in the coming solar maximum.

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

Effects of error in code transition levels on nonlinearity and effective number of bits (ENOB) of an analog to digital converter (ADC) are presented in this article. Error in code transition level is determined by deviation of code transition levels from the mean of the estimated code transition levels. Errors in estimate of differential nonlinearity (DNL), integral nonlinearity (INL) and ENOB are computed by considering error in code transition levels and computing corresponding values. In this study, 5- and 8-bit ADC transfer characteristics are simulated and arbitrary nonlinearity errors are introduced. Suitable corrections are applied in code transition levels and computation of estimate of nonlinearity with and without corrections are reported. Results have been compared with earlier published work and improvements are observed. Effects of overdrive and additive noise on ENOB for 5-bit ADC are also reported.

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

The readout of silicon strip sensors in the upgraded Tracker System of Large Hadron Collider beauty (LHCb) experiment will require a novel complex Application Specific Integrated Circuit (ASIC). The ASIC will extract and digitise analogue signal from the sensor and subsequently will perform digital processing and serial data transmission.One of the key processing blocks, placed in each channel, will be an Analogue to Digital Converter (ADC). A prototype of fast, low-power 6-bit Successive Approximation Register (SAR) ADC was designed, fabricated and tested. The measurements of ADC prototypes confirmed simulation results showing excellent overall performance. In particular, very good resolution with Effective Number Of Bits (ENOB) 5.85 was obtained together with very low power consumption of 0.35 mW at 40 MS/s sampling rate. The results of the performed static and dynamic measurements confirm excellent ADC operation for higher sampling rates up to 80 MS/s.

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm2 in the 0.13-μm CMOS process.

The paper is devoted to methods of accurate assessment of expected and real effective number of bits (ENOB) of cyclic A/D converters. There is discussed the equivalence of definition of ENOB in IEEE Standard 1241-2000 and analytical definition of ENOB used in our previous works. Generalization of ENOB definition is discussed, which enables its accurate application to analysis and testing of the cyclic and pipe-line ADCs performance. The indirect and direct methods of ENOB assessment are discussed. The results of the paper can be used for development of reliable procedures for analysis and testing of ADC performance.

This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with 0.18μm complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

A 5 GHz-band direct digital radio frequency (RF) modulator using current-mode digital-to-analog converter (DAC) with idle current is proposed and fabricated in 90-nm complementary metal oxide semiconductor (CMOS) process. Since the proposed modulator directly converts digital base band (BB) parallel input signal into RF signal, small die size and low dc operation can be achieved. To reduce the higher order distortion components at the RF output, idle current is provided to BB current output from the current-mode DAC. By providing idle current of 10% of full scale DAC output current, 2nd and 3rd order distortion components near 5 GHz-band carrier are reduced and the improvement of effective number of bits (ENOB) is achieved. Measured ENOB of 6.36 bit (spurious-free dynamic range (SNDR) of 40.0 dB) with RF modulated output power of -28.4 dBm is obtained at 5 GHz. The core size of the proposed modulator integrated circuit (IC) is 200μm × 200μm. The dc power consumption of core circuit excluding inverter section for digital BB signal converter is 2.5 mW (2.1 mA/1.2 V).

In-Band Full-Duplex (IBFD) Underwater Acoustic (UWA) communication technology can transmit and receive communication signals in the same frequency band at the same time. Theoretically, its frequency utilization efficiency can reach twice of the traditional half-duplex (HD) UWA communication systems. Therefore, it holds great research significance and application value for UWA communication where available spectrum resources are seriously limited. The main challenge in the implementation of IBFD-UWA communication system is to counteract the local self- interference (SI) signal. Generally, SI cancellation (SIC) can be divided into three main aspects, namely, SI suppression in space, SIC in analog domain and digital domain. Digitally Assisted Analog SIC (DAA-SIC) is concerned as it can deal with complexSI propagation channel. However, in the implementation process of the DAA-SIC scheme, its performance will be affected by hardware conditions, such as the effective number of bits of analog to digital converter (ADC) of auxiliary acquisition link, non-linear distortion of power amplifier (PA) and so on. To deal with the influence of hardware parameters on the performance of DAA-SIC scheme, this paper proposes a new analog SIC scheme. The core of this scheme is to reconstruct the output signal of PA and reduce the non-linear distortion of power amplifier and the influence of effective number of bits of auxiliary link through Memory Polynomial (MP) model and Digital Pre- Distortion (DPD) process. The performance of the existing scheme and the new DAA-SIC scheme is verified by numerical simulation. The simulation results show the effectiveness of the proposed scheme.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.