A broadband digital receiving system with large dynamic range for solar radio observation

We have designed, manufactured, and characterized an 8-bit 5 Giga samples per second (Gsps) ADC printed circuit board assembly (PCBA). An e2v EV8AQ160 ADC chip was used in the design and the board is plug compatible with the field programmable gate array (FPGA) board developed by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) community. Astronomical interference fringes were demonstrated across a single baseline pair of antennas using two ADC boards on the Yuan Tseh Lee Array for Microwave Background Anisotropy (AMiBA) telescope. Several radio interferometers are using this board for bandwidth expansion, such as Submillimeter Array; also, several experimental telescopes are building new spectrometers using the same board. The ADC boards were attached directly to the Reconfigurable Open Architecture Computing Hardware (ROACH-2) FPGA board for processing of the digital output signals. This ADC board provides the capability of digitizing radio frequency signals from DC to 2 GHz (3 dB bandwidth), and to an extended bandwidth of 2.5 GHz (5 dB) with derated performance. The following worst-case performance parameters were obtained over 2 GHz: spur free dynamic range (SFDR) of 44 dB, signal-to-noise and distortion (SINAD) of 35 dB, and effective number of bits (ENOB) of 5.5.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

SummaryThis paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.

This paper presents a 10-bit 100MS/s analog to digital converter (ADC) that based on successive approximation (SAR) algorithm. This ASIC is to fulfill the requirement of Hadronic Calorimeter (HCal) upgrade: custom cost-efficient high sampling digitizer electronics and capable of continuous operation mode. The designed chip is developed by using the TSMC 65nm CMOS technology. The post-layout simulations show this ADC could achieve peak signal to noise and distortion ratio (SNDR) of 58 dB at Nyquist rate input frequency and power consumption of 3.5 mW. The peak effective number of bits (ENOB) is 9.6 bits, equivalent to the figure of merit of 45 fJ/conversion step.

To meet the demand for high-precision biological signal detection in wearable biomedical devices, this paper proposes the design of a fourth-order discrete-time sigma–delta analog-to-digital converter (ADC) employing a multi-stage noise shaping (MASH) 2-2 architecture. In the first-stage sub-modulator, the first integrator adopts a double-sampling structure, which improves noise shaping performance markedly. A novel common-mode feedback (CMFB) circuit has also been designed, which addresses the phase-dependent loading issue in traditional switched-capacitor networks. Notably, a dynamically activated nonuniform quantization mode is innovatively proposed in the second stage. It integrates 2.5-bit coarse quantization with 2-bit fine quantization in specific intervals, enabling high-precision detection of the small-amplitude quantization errors from the first-stage sub-modulator. In addition, the comparator in this stage integrates feed-forward summation capability and retains input offset voltage storage (IOS) technology to reduce the offset voltage. Meanwhile, the designs of dynamically activated nonuniform quantizer and comparator with integrated summation function have reduced the power consumption of the modulator by 19%. In a 180-nm CMOS process, the modulator occupies a layout area of 0.57[Formula: see text]mm 2 and simulation results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 113.2[Formula: see text]dB. After processing by the cascaded integrator comb (CIC) decimation filter, the ADC achieves a peak SNDR of 115.6[Formula: see text]dB, an effective number of bits (ENOB) of 18.91 bits and a power consumption of 4.36[Formula: see text]mW under a 1.8[Formula: see text]V supply. These performance metrics correspond to a state-of-the-art figure-of-merit (FoM) of 175.1[Formula: see text]dB.

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

The static maximum relative error of the ADC for sensors is determined by the value of its least significant bit. During the input signal conversion in the ADC the information delay causes the dynamic error, which is added to the static error and actually reduces the effective number of bits. This decrease can be estimated by the effective number of bits, which illustrates the qualitative and quantitative assessment of the additional error. The article demonstrates that the effective bits rate is defined by the delay period of information in the ADC, as well as the sampling rate of the input signal. This, in turn, requires setting the spectrographic density (SD) for the converted signal, as well as an algorithm for selecting the sampling rate. It is recommended that the delay time of the ADC includes the delay in the analog storage and amplitude multiplexer, which are located at the ADC input and are directly involved in the conversion process. The article draws attention to the fact that the real sampling rate of analog signals, chosen from the point of view of the straight task of errors distribution in the automatic control system, significantly exceeds the sampling rate according to the sampling theorem. This requires the correction of the obtained results using the sampling theorem, in the direction of reduction of effective number of bits.

To keep pace with increasing data rates in the worldwide communication networks and the increased bandwidths requirements in measurement devices, sensors, radar, and many other applications, photonics-assisted analog-to-digital converters (PADCs) may be promising alternatives to circumvent the bandwidth bottleneck in pure electronic analog-to-digital converters (EADCs). Here we analyze optical sub-Nyquist orthogonal sampling with sinc-pulse sequences for the time-interleaving of high-bandwidth input signals into parallel low-bandwidth sub-signals (first sampling stage). These sub-signals are then detected and further processed with low-bandwidth electronic devices in parallel branches (second sampling stage). Orthogonal sampling with ideal devices is error-free. Additionally, in contrast to electronic sample and hold circuits, the first sampling stage is based on a multiplication and not a switching. Therefore, it adds no aperture jitter and the low jitter of today's oscillators can be directly transferred to the sampling of high-bandwidth signals. Compared to the direct detection, in simulations and a proof of concept experimental demonstration, we show around 8.5 dB signal-to-noise and distortion (SINAD) and 1.4 bit effective number of bits (ENOB) improvement for the detection of a 14.5 GHz signal with the proposed method in a three-branch system. With further simulations we analyze the possibilities and limits of the method and derive an equation for the resolution. In a nine-branch system with a jitter of 10 fs for the oscillator and 100 fs for the electronics, 100 GHz input signals can be processed with a resolution of 6 bit in 11 GHz electronics, for instance. The scheme is only based on a modulator and standard RF equipment. Therefore, integration into a single chip, together with the following electronic ADCs is straightforward.

A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications

We characterize the performance of a highly parallel pulsed optoelectronic analog to digital converter. The system is based on a time-domain to wavelength-domain mapping, such that an input analog signal is parallelized using a wavelength-division-demultiplexed scheme. Each parallel wavelength channel is then digitized using conventional, slow electronic analog-digital converters. We use narrow-band signals up to 18 GHz and histogram testing to characterize the system. From the measurements, we deduce the effective number of bits of the system to be /spl sim/6 and /spl sim/5 bits for 4 and 36 giga-samples-per-second (GSPS) sampling rates, respectively.

This paper introduces a 12-bit sub-radix successive approximation register (SAR) analog-to-digital converter (ADC) operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 0 0 ~ MS/s}$</tex>. The design employs an optimized digital control logic with a reduced delay path to enhance conversion speed; meanwhile, shortening the decision time in the SAR algorithm increases susceptibility to comparator instability or settling of capacitor digital-to-analog (CDAC). To mitigate this, a redundancy bit is implemented to correct erroneous decisions. The proposed architecture achieves a signal-to-noise-and-distortion ratio (SNDR) over 70 dB, corresponding to an effective number of bits (ENOB) of 11 at the Nyquist rate, and consumes 2.85 mW with a 1.2 V power supply.

In quantum precision measurement applications–where low-amplitude signal fluctuations must be detected with the highest accuracy–precise conversion of low-frequency analog inputs is essential. Nonlinearity and phase noise in voltage-controlled oscillators (VCOs) are known to limit the linearity and accuracy of VCO-based analog-to-digital converters (VCO-ADCs). In this work, we employ an LC-VCO with intrinsically low phase noise in combination with a closed-loop differential pulse-code modulation (DPCM) feedback architecture to mitigate both phase noise and nonlinearity. Specifically, a controlled bias is applied to the VCO input using asynchronous Graycode counting and a digital predictor, enabling compression of the VCO input dynamic range. Combined with first-order noise shaping and a moderate oversampling ratio, this approach achieves a high dynamic range without resorting to higher-order loop designs. The system integrates a differential LC-VCO module, a low-jitter clock source, a precision amplifier, and a high-resolution DAC. Experimental results demonstrate a spurious-free dynamic range (SFDR) of 109 dB and a signal-to-noise-and-distortion ratio (SNDR) of 104 dB, corresponding to a 17-bit effective number of bits (ENOB), over a 100 Hz bandwidth.

Digitally-assisted integrated circuit design has gained popularity in recent years due to challenges associated with analog components in mixed-signal systems-on-a-chip, which include process variations, mismatches, and increased demand for circuit complexity in sub-micron fabrication process technologies. To optimize efficiency and cost, the focus during hardware design is increasingly directed on the creation of reliable and robust circuits that are immune to variations and unpredictable factors out of the designer's control. On the other hand, the circuits should be power and area efficient to adapt to the needs associated with portable devices, wireless communications, and the global energy and cost saving trends. On-chip calibration techniques can be developed to address these issues by reducing the sensitivity of analog circuit designs, thereby improving their universal usefulness and scalability. Another emerging trend is the rising demand for high-speed low-power analog-to-digital converters (ADCs) to accommodate the increased use of digital processing and big data. The research described in this thesis unites these topics in a design approach for ADCs. This thesis introduces the design of a 3-bit flash ADC with an offset calibration scheme, which is integrated into a two-step 8-bit hybrid flash/successive approximation register (SAR) architecture with time-interleaving. Due to the hybrid architectural structure, the offset requirement for the flash ADC is more stringent than for a conventional standalone 3-bit ADC. Two pairs of transistors are employed to adjust the offsets for each of the seven comparators in the flash ADC by creating a current flow imbalance between the comparator's branches. The amount of current injected in each branch is controlled through the gate voltages of the calibration transistors, which are generated with automatic on-chip calibration circuitry that was developed as part of this research. The circuits were designed, simulated, and fabricated using 130nm complementary metal-oxide semiconductor (CMOS) technology. The calibration path emulates the ADC's normal operation to establish realistic loading and transient effects. Furthermore, the design approach addresses integration challenges within the hybrid ADC system, such as kickback noise and common-mode variations. Monte Carlo simulation results show that the offset standard variation is reduced from 19.2mV to 0.582mV through the calibration. The power consumption of all digital circuits is 1.36mW from a separate 1.2V supply, and the power consumption of the calibration logic with a 10MHz clock is 0.60mW. The dynamic latched comparator of the flash ADC with kickback reduction was evaluated with post-layout simulations including process-voltage-temperature (PVT) variations. It has a 231ps propagation delay, and consumes 0.16mW. From simulations of the flash ADC, the worst-case effective number of bits (ENOB) is 2.88, and the worst-case signal-to-noise-and-distortion ratio (SNDR) is 19.1dB in the slow process corner case with a temperature of 85 degree Celsius and 1.14V supply. The flash ADC consumes 3.6mW. The comparator design incorporates a kickback reduction technique that reduces the kickback effect from 23.3mV to 1.2mV for a 500mV input during system-level simulations. Measurements of a prototype chip show that the ENOB improves from 3.64 to 5.24 bits using a 500MHz clock during automatic calibration.