A High-Resolution LC-VCO-Based ADC for Low-Frequency Signal Measurement

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

SummaryThis paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.

A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications

Since the conventional figure of merit (FOM) neglects the flicker-noise effect in a voltage-controlled oscillator (VCO), we devised a new FOM that considers the flicker-noise effect and, thus, allows phase noise (which is dominated by flicker noise) of different VCOs to be compared. Using the proposed FOM, we analyze the phase noise and power dissipation in an inverter-based ring oscillator, since it has a simple topology and few noise sources. From this analysis, we draw three conclusions: first, varying load capacitance changes oscillation frequency only without changing proposed FOM; second, to improve the proposed FOM, large transistor length should be chosen, third, comparing FOM of a VCO and FOM calculated from target specifications of phase noise and power dissipation shows that the designed VCO meets target specifications. This second and third conclusion is useful for easily designing an actual inverter-based quadrature-ring VCO. A prototype inverter-based quadrature-ring VCO was fabricated by using 0.18-μm CMOS technology with an active die area of 0.018 mm2. It consumes 2.61 mW from a 1.8-V power supply. Moreover, it has an oscillation frequency of 338.5 MHz, phase noise of -110 dBc/Hz at 1-MHz offset frequency, and proposed FOM of 160.4 dB (at 0.1-MHz offset frequency).

This study was devoted to oscillator noise analysis and simulation in order to apply it on VCOs (Voltage Controlled Oscillator) for Intermediate Frequency integrated circuits, especially for TV receivers. An original period jitter transient simulation method, thanks to the transient noise simulator in ELDO and to a period extractor (ELDO-FAS based language software) has been worked out, making it is possible to deduce the VCO phase noise.With this kind of simulation, it is possible to evaluate the effect of the various noise sources in the VCO on the period jitter. Two VCOs, with optimized phase noise, have been designed for Intermediate Frequency integrated circuits. The first VCO, using a LC (inductance - capacitance) resonant architecture(the inductance is located outside the integrated circuit) has been designed and implemented. The frequency variation is produced by a variable capacitance. One of the major defects of the variable capacitor (parasitic phase displacement of the capacitive current) has been originally compensated. This VCO phase noise has been measured, simulated in many ways, with a good correlation. The period jitter simulation methodology has been so validated. A second VCO, of relaxation kind, completely integrated (it does not need any external element), dedicated to replace the first one, has been designed. Its architecture is based on RC (resistance - capacitance) elements in differential mode. It is able to operate with a low power supply (5V). Its phase noise has been optimized thanks to the previous methodology.

CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5 V, 0.25 /spl mu/ CMOS PLL clock generator with a lock range of 100 MHz-400 MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with 0.18μm complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

This paper presents the design and characterization of a negative resistance type 1.9-GHz oscillator using high quality factor (Q) embedded lumped-element LC passives in an organic-based substrate with liquid crystalline polymer (LCP) dielectric material. A design strategy using analytical models is implemented to determine the value of the base inductance subject to the constraints set by power dissipation. Additionally, the effect of component Qs on the phase noise is qualitatively discussed. This paper also addresses the effects of the parasitics of the surface-mount active devices on the noise spectrum of a negative resistance type voltage-controlled oscillator (VCO). The designed VCO is fully embedded in the LCP substrate and uses high Q on-package passive components. The VCO was measured to operate at 1.92 GHz dissipating 14 mW of dc power and measured a phase noise of -118dBc/Hz and -133 dBc/Hz at 600 KHz and 3-MHz offset, respectively. The high Q of the LC tank circuit was utilized to optimize the VCO to operate from a 2-V supply at bias current of 0.9 mA. Finally, the design and implementation issues in a 2.25-GHz Colpitt's oscillator on LCP substrate are shown. The effects of scaling capacitance ratio on VCO phase noise and on power consumption are verified for the Colpitt's oscillator

Solar radio spectra and their temporal evolution provide important clues to understand the energy release and electron acceleration process in the corona, and are commonly used to diagnose critical parameters such as the magnetic field strength. However, previous solar radio telescopes cannot provide high-quality data with complete frequency coverage. Aiming to develop a generalized solar radio observing system, in this study, we designed a digital receiving system that could capture solar radio bursts with a broad bandwidth and a large dynamic range. A dual-channel analog-to-digital converter (ADC) printed circuit board assembly (PCBA) with a sampling rate of 14-bit, 1.25 Giga samples per second (GSPS) cooperates with the field-programmable-gate-array (FPGA) chip XC7K410T in the design. This receiver could realize the real-time acquisition and preprocessing of high-speed data of up to 5 GB s−1, which ensures high time and spectral resolutions in observations. This receiver has been used in the solar radio spectrometer working in the frequency range of 35 to 40 GHz in Chashan Solar Observatory (CSO) established by Shandong University, and will be further developed and used in the solar radio interferometers. The full-power bandwidth of the PCBA in this receiving system could reach up to 1.5 GHz, and the performance parameters (DC–1.5 GHz) are obtained as follows: spur free dynamic range (SFDR) of 64.7–78.4 dB, signal-to-noise and distortion (SINAD) of 49.1–57.2 dB, and effective number of bits (ENOB) of > 7.86 bit. Based on the receiver that we designed, real-time solar microwave dynamic spectra have been acquired and more solar microwave bursts with fine spectral structures are hopeful to be detected in the coming solar maximum.

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

A continuous-time quadrature band pass sigma-delta (a#x03C3;a#x03B4;) modulator consisting of a chain of integrators with weighted capacitive feed forward summation (CICFF) topology is presented for long-term evolution (LTE) network optimization and green application. The main advantage of the proposed modulator adopts the weighted capacitor technology to save a feed forward summation amplifier, hence reduces power consumption. The chip was implemented in TSMC 0.18 a#x03BC;m CMOS process. Low Noise Amplifier for the reduction of components is used in this LNA. Integrated Green single-stage of LNA is using series-peaking technology for low power requirement. With a 1.8 V supply voltage, a sampling rate of 200 MSamples/s and an input sinusoid of-1.0 dBm at 1 MHz, measured results have achieved a spurious-free dynamic range (SFDR) of 42 dB, a dynamic range (DR) of 56 dB, a peak SNDR of 57.86 dB, an effective number of bits (ENOB) of 9.3-bit over 5 MHz signal bandwidth and a power dissipation of 21.8 mW for green computing and communication application.