A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones

Dual-frequency piezoelectric microelectromechanical systems (MEMS) microphones based on highly doped AlSc30%N thin films are developed for aeroacoustic measurements with high sensitivity, wide bandwidth, and large dynamic range. Comparing with the previous version based on lead zirconate titanate (PZT) thin films, the sensitivity of AlSc30%N based dual frequency MEMS microphones is significantly improved and no direct current bias is required for the new AlSc30%N material. The microfabrication, packaging, and testing of MEMS microphones with two pairs of triangular cantilevers were conducted using the cleanroom facilities and characterization tools. The MEMS die structure was characterized by a focused ion beam scanning electron microscopy (FIB-SEM). The resonant frequencies and mode shapes of large and small cantilevers were measured by laser Doppler vibrometer (LDV) to evaluate their mechanical performance. The aeroacoustic characterizations were conducted at the BACCHUS test bench in Airbus. The sensitivity of 3.2mV/[email protected], signal-to-noise ratio (SNR) of 60.2 dB (ref. 94 dB SPL, 30kHz), frequency range up to 55 kHz, and dynamic range up to 147 dB SPL were obtained in the first preliminary test. The MEMS microphone samples were also acoustically characterized within high-speed air flow. The overall performance of the dual-frequency piezoelectric MEMS microphones based on AlSc30%N thin films is better than the state-of-the-art microphones taking into account key parameters such as form factor, acoustic performance, and product price.

A unidirectional microelectromechanical system (MEMS) microphone single module for handsfree and voice recognition systems in automobiles is presented. Because in-cabin noise and temperature variation affect the reduction in the handsfree and voice recognition system performance, noise suppression and increasing the signal-to-noise ratio (SNR) of the microphone are required. In this study, a capacitive MEMS microphone module with a high SNR and a unidirectional characteristic is achieved by designing the structure, package, and module of the MEMS microphone. To improve the SNR, the microphone is developed using a slit-edged membrane. The slit structure is designed to release the residual stress of the membrane to achieve improved sensitivity and SNR. The unidirectional characteristic of the microphone enables suppression of noise signals from undesired directions. The directional characteristic of the microphone is realized by attaching a porous SU-8 filter to delay the time to one of the two acoustic ports on the package. Tests on the proposed unidirectional MEMS microphone package and module show that an SNR of 62.4 dB and a front-back ratio of 27.1 dB are achieved.

Fabrication and acoustic performance of a microelectromechanical systems (MEMS) microphone are presented. The microphone uses an unusual electrostatic sensing scheme that causes the sensing electrode to move away, or levitate, from the biasing electrode as the bias voltage is applied. This approach differs from existing electrostatic sensors and completely avoids the usual collapse known as pull-in instability. In this study, our goal is to fabricate a MEMS microphone whose sensitivity could be improved simply by increasing the bias voltage, without suffering from pull-in. The microphone is successfully fabricated and tested in our anechoic chamber. A read-out circuit is used to obtain electrical signals in response to sound pressure at various bias voltages. Experimental results show that the sensitivity increases approximately linearly with bias voltage for bias voltages from 40 volts to 100 volts. The ability to design electrostatic sensors without concerns about pull-in failure permits a wide range of promising sensor designs.

Impact-Echo (IE) is a nondestructive testing technique for plate like concrete structures. We propose a new sensor concept for air-coupled IE measurements. By using an array of MEMS (micro-electro-mechanical system) microphones, instead of a single receiver, several operational advantages compared to conventional sensing strategies in IE are achieved. The MEMS microphone array sensor is cost effective, less sensitive to undesired effects like acoustic noise and has an optimized sensitivity for signals that need to be extracted for IE data interpretation. The proposed sensing strategy is justified with findings from numerical simulations, showing that the IE resonance in plate like structures causes coherent surface displacements on the specimen under test in an area around the impact location. Therefore, by placing several MEMS microphones on a sensor array board, the IE resonance is easier to be identified in the recorded spectra than with single point microphones or contact type transducers. A comparative measurement between the array sensor, a conventional accelerometer and a measurement microphone clearly shows the suitability of MEMS type microphones and the advantages of using these microphones in an array arrangement for IE. The MEMS microphone array will make air-coupled IE measurements faster and more reliable.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25~^{\circ }$ </tex-math></inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$ </tex-math></inline-formula>C, and below 0.74 dB over supply variations of ±5%.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

A linearization technique of voltage-to-frequency characteristics of voltage-controlled oscillator (VCO) analog-to-digital converters (ADCs) is presented. In contrast to previous works, the proposed technique is an open-loop calibration-free configuration, so it can operate at higher frequencies. It is also independent of the delay element structure, so it can be applied to various VCO ADC topologies. The analog input signal is first mapped through a preweighted resistor network in which every delay element experiences a different version of the input and produces the corresponding delay. As a result, the proposed approach suppresses the impact of V/F nonlinearity on the ADC performance by expanding a linear region of the transfer curve over the full rail-to-rail input. This technique shows substantial improvement results by keeping nonlinearity within ±0.5% over the full input scale (dBFS) and achieves a peak signal-to-noise and distortion ratio (SNDR) of 75.7 and 60.4 dB for input of -8 and 0 dBFS, respectively.

Preparing and pre-testing experimental setups for flight tests is a lengthy but necessary task. One part of this preparation is comparing newly available measurement technology with proven setups. In our case, we wanted to compare acoustic Micro-Electro-Mechanical Systems (MEMS) to large and proven surface-mounted condenser microphones. The task started with the comparison of spectra in low-speed wind tunnel environments. After successful completion, the challenge was increased to similar comparisons in a transonic wind tunnel. The final goal of performing in-flight measurements on the outside fuselage of a twin-engine turboprop aircraft was eventually achieved using a slim array of 45 MEMS microphones with additional large microphones installed on the same carrier to drawn on for comparison. Finally, the array arrangement of MEMS microphones allowed for a complex study of fuselage surface pressure fluctuations in the wavenumber domain. The study indicates that MEMS microphones are an inexpensive alternative to conventional microphones with increased potential for spatially high-resolved measurements even at challenging experimental conditions during flight tests.

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC

In quantum precision measurement applications–where low-amplitude signal fluctuations must be detected with the highest accuracy–precise conversion of low-frequency analog inputs is essential. Nonlinearity and phase noise in voltage-controlled oscillators (VCOs) are known to limit the linearity and accuracy of VCO-based analog-to-digital converters (VCO-ADCs). In this work, we employ an LC-VCO with intrinsically low phase noise in combination with a closed-loop differential pulse-code modulation (DPCM) feedback architecture to mitigate both phase noise and nonlinearity. Specifically, a controlled bias is applied to the VCO input using asynchronous Graycode counting and a digital predictor, enabling compression of the VCO input dynamic range. Combined with first-order noise shaping and a moderate oversampling ratio, this approach achieves a high dynamic range without resorting to higher-order loop designs. The system integrates a differential LC-VCO module, a low-jitter clock source, a precision amplifier, and a high-resolution DAC. Experimental results demonstrate a spurious-free dynamic range (SFDR) of 109 dB and a signal-to-noise-and-distortion ratio (SNDR) of 104 dB, corresponding to a 17-bit effective number of bits (ENOB), over a 100 Hz bandwidth.

Microphones fabricated using microelectromechanical systems (MEMS) technology are one of the fastest growing applications of MEMS. While most commercial MEMS microphones are sensed capacitively, piezoelectric MEMS microphones require less accompanying electronics and offer increased linearity. Currently, piezoelectric MEMS microphones suffer from high noise levels, limiting their applicability. This paper presents an alternative sensor geometry consisting of a cantilever beam electrostatically clamped to the center of a diaphragm that both favorably concentrates stress from the applied acoustic load and eliminates the deleterious effects of residual stress in the piezoelectric material. A complete analysis of the sensitivity and noise characteristics of the electromechanical design (including the amplifying electronics) is performed and compared to a design employing a piezoelectric layer on a diaphragm. The analysis has shown that the proposed geometry can be used to build microphones sensed via aluminum nitride with noise levels around 48 dBA while similar materials and sizes result in noise levels around 57 dBA using the standard geometry.

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$</tex-math> </inline-formula> -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

A 10-bit 20-Msample/s CMOS pipelined analog-to-digital converter (ADC) is proposed, which is implemented in a 0.6/spl mu/m double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMCs library of 0.6/spl mu/m mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 5MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.