Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper proposes a leading-subcycles capacitor error-averaging (LCEA) scheme to reduce the capacitor mismatch error of cyclic analog-to-digital converters (ADCs) while only slightly lowering the conversion rate. The scheme does not need complicated structures or extra calibration circuits. Hence, the proposed LCEA scheme can be used for cyclic ADCs to achieve high accuracy while maintaining their low-power and small-area features. In addition, the figure of merit (FOM) versus the number of averaging operations in a complete conversion cycle is analyzed such that power-accuracy-speed tradeoffs can be optimized. A proof of concept 12-bit cyclic ADC is implemented to compare the performance of the proposed LCEA scheme with that of a conventional cyclic ADC. The chip is fabricated in a 3.3-V, 0.35-μm CMOS process. Measurements demonstrate that the cyclic ADC with only two averaging operations has a 6 dB and 10 dB higher signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, than the conventional cyclic ADC, and with only a slightly reduced conversion rate of 12/13 times than that of the conventional cyclic ADC. In addition, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional scheme which indicates the advantage of the LCEA technique.

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$</tex-math> </inline-formula> -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

A linearization technique of voltage-to-frequency characteristics of voltage-controlled oscillator (VCO) analog-to-digital converters (ADCs) is presented. In contrast to previous works, the proposed technique is an open-loop calibration-free configuration, so it can operate at higher frequencies. It is also independent of the delay element structure, so it can be applied to various VCO ADC topologies. The analog input signal is first mapped through a preweighted resistor network in which every delay element experiences a different version of the input and produces the corresponding delay. As a result, the proposed approach suppresses the impact of V/F nonlinearity on the ADC performance by expanding a linear region of the transfer curve over the full rail-to-rail input. This technique shows substantial improvement results by keeping nonlinearity within ±0.5% over the full input scale (dBFS) and achieves a peak signal-to-noise and distortion ratio (SNDR) of 75.7 and 60.4 dB for input of -8 and 0 dBFS, respectively.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

To meet the demand for high-precision biological signal detection in wearable biomedical devices, this paper proposes the design of a fourth-order discrete-time sigma–delta analog-to-digital converter (ADC) employing a multi-stage noise shaping (MASH) 2-2 architecture. In the first-stage sub-modulator, the first integrator adopts a double-sampling structure, which improves noise shaping performance markedly. A novel common-mode feedback (CMFB) circuit has also been designed, which addresses the phase-dependent loading issue in traditional switched-capacitor networks. Notably, a dynamically activated nonuniform quantization mode is innovatively proposed in the second stage. It integrates 2.5-bit coarse quantization with 2-bit fine quantization in specific intervals, enabling high-precision detection of the small-amplitude quantization errors from the first-stage sub-modulator. In addition, the comparator in this stage integrates feed-forward summation capability and retains input offset voltage storage (IOS) technology to reduce the offset voltage. Meanwhile, the designs of dynamically activated nonuniform quantizer and comparator with integrated summation function have reduced the power consumption of the modulator by 19%. In a 180-nm CMOS process, the modulator occupies a layout area of 0.57[Formula: see text]mm 2 and simulation results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 113.2[Formula: see text]dB. After processing by the cascaded integrator comb (CIC) decimation filter, the ADC achieves a peak SNDR of 115.6[Formula: see text]dB, an effective number of bits (ENOB) of 18.91 bits and a power consumption of 4.36[Formula: see text]mW under a 1.8[Formula: see text]V supply. These performance metrics correspond to a state-of-the-art figure-of-merit (FoM) of 175.1[Formula: see text]dB.

This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta–sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma$ </tex-math></inline-formula> ) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2–2 MASH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40° to 125° and within 2-dB SNDR degradation for frequency variations of 20% range.

A 6-bit 2.5-GS/s $8\times $ dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s.

A 10-bit 20-Msample/s CMOS pipelined analog-to-digital converter (ADC) is proposed, which is implemented in a 0.6/spl mu/m double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMCs library of 0.6/spl mu/m mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 5MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.

In quantum precision measurement applications–where low-amplitude signal fluctuations must be detected with the highest accuracy–precise conversion of low-frequency analog inputs is essential. Nonlinearity and phase noise in voltage-controlled oscillators (VCOs) are known to limit the linearity and accuracy of VCO-based analog-to-digital converters (VCO-ADCs). In this work, we employ an LC-VCO with intrinsically low phase noise in combination with a closed-loop differential pulse-code modulation (DPCM) feedback architecture to mitigate both phase noise and nonlinearity. Specifically, a controlled bias is applied to the VCO input using asynchronous Graycode counting and a digital predictor, enabling compression of the VCO input dynamic range. Combined with first-order noise shaping and a moderate oversampling ratio, this approach achieves a high dynamic range without resorting to higher-order loop designs. The system integrates a differential LC-VCO module, a low-jitter clock source, a precision amplifier, and a high-resolution DAC. Experimental results demonstrate a spurious-free dynamic range (SFDR) of 109 dB and a signal-to-noise-and-distortion ratio (SNDR) of 104 dB, corresponding to a 17-bit effective number of bits (ENOB), over a 100 Hz bandwidth.

A low-power, small-area, and medium-resolution analog-to-digital converter (ADC) is one of the critical building blocks in a system-on-chip (SoC). But it is also a primary bottleneck of SoC time-to-market due to full custom design. To improve design efficiency, the digital synthesis tools are employed to accelerate its layout design as long as the ADC mostly consists of digital standard cells and can be described in Hardware Description Languages (HDLs). This kind of ADC is called as synthesizable ADC [1–2], in which a voltage-controlled oscillator (VCO)-based ADC has become a popular choice because of its high digitization. However, the open-loop VCO-based ADC suffers from the inherent nonlinearity of VCO and necessitates calibration [3]. A closed loop is adopted to suppress the nonlinearity [4], but requires a feedback scheme with a digital-to-analog converter (DAC). A bi-level feedback scheme in the digital style is proposed in [5], but it ignores the lead-lag status between dual VCO. A tri-level feedback scheme is proposed in [6] to make full use of the phase resolution. However, it is designed in the analog style and hard to synthesize due to analog circuitry, including analog switches and reference generators.

This paper presents a new single channel 6-bit 900MS/s asynchronous binary search analog to digital converter (ADC). The proposed ADC works based on binary search principle like the Successive Approximation Register (SAR) ADC. Compared to SAR ADC the speed is improved significantly adopting two design techniques. By implementing the binary search in an open loop configuration using asynchronous clock generation the delay in the feedback path of the SAR ADC is relaxed significantly. Moreover in the proposed asynchronous binary search ADC two bits are resolved in each stage of the ADC. By resolving two bits in each stage the proposed ADC can operate twice as fast as conventional asynchronous binary search ADCs. The proposed single channel 6-bit 900MS/s ADC was designed in 90nm CMOS process. Simulation results show that the proposed ADC reaches a peak SNDR of 35.82dB consuming 4.33mW from a single 1.2V power supply. It achieves of 95.3fJ/conv.code FoM.