A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

This article presents an intrinsically linear continuous-time (CT) zoom analog-to-digital converter (ADC) architecture that uses a coarse first-order CT delta-sigma modulator (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M) followed by a fine third-order CT-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M. The 1.5-bit output of the coarse CT-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M is filtered by an 8-tap finite impulse response (FIR) filter, and then, a current-steering DAC provides intrinsically linear outputs to the fine <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M. The associated delay is mitigated by increasing the coarse sampling rate by a factor of 4. The coarse <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M significantly relaxes the requirements of the fine <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M, but despite the faster sampling rate, consumes negligible power, because its noise is canceled for the final output, allowing the use of a relatively large input resistor. The ADC prototype fabricated in a 65-nm CMOS process occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.124~{\text {mm}^{{2}}}$ </tex-math></inline-formula> and consumes only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$243~{\mu }$ </tex-math></inline-formula>W from a 1.2-V supply. It achieves 92.0-dB signal-to-noise and distortion ratio (SNDR), 92.3-dB signal-to-noise ratio (SNR), 97.4-dB dynamic range (DR), and 105.7-dB spurious-free DR (SFDR) over a 50-kHz bandwidth without using DAC linearization or calibration. This corresponds to Schreier FoMs of 175.1 dB (SNDR) and 180.5 dB (DR).

To meet the demand for high-precision biological signal detection in wearable biomedical devices, this paper proposes the design of a fourth-order discrete-time sigma–delta analog-to-digital converter (ADC) employing a multi-stage noise shaping (MASH) 2-2 architecture. In the first-stage sub-modulator, the first integrator adopts a double-sampling structure, which improves noise shaping performance markedly. A novel common-mode feedback (CMFB) circuit has also been designed, which addresses the phase-dependent loading issue in traditional switched-capacitor networks. Notably, a dynamically activated nonuniform quantization mode is innovatively proposed in the second stage. It integrates 2.5-bit coarse quantization with 2-bit fine quantization in specific intervals, enabling high-precision detection of the small-amplitude quantization errors from the first-stage sub-modulator. In addition, the comparator in this stage integrates feed-forward summation capability and retains input offset voltage storage (IOS) technology to reduce the offset voltage. Meanwhile, the designs of dynamically activated nonuniform quantizer and comparator with integrated summation function have reduced the power consumption of the modulator by 19%. In a 180-nm CMOS process, the modulator occupies a layout area of 0.57[Formula: see text]mm 2 and simulation results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 113.2[Formula: see text]dB. After processing by the cascaded integrator comb (CIC) decimation filter, the ADC achieves a peak SNDR of 115.6[Formula: see text]dB, an effective number of bits (ENOB) of 18.91 bits and a power consumption of 4.36[Formula: see text]mW under a 1.8[Formula: see text]V supply. These performance metrics correspond to a state-of-the-art figure-of-merit (FoM) of 175.1[Formula: see text]dB.

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achieving enhanced resolution and improved linearity with little power consumption is possible. Additionally, several energy-efficient techniques are adopted. Fabricated in 55-nm CMOS, the prototype occupies 0.36mm2 active area and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$188.6\mu $ </tex-math></inline-formula>W from a 1.2-V supply. The implemented CT-IADC achieves a measured dynamic range (DR) of 96.5 dB and a signal-to-noise-and-distortion ratio (SNDR) of 95.4 dB for a maximum input of 1.9Vpp and a bandwidth of 20kHz. The measured SNDR-based Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula>) is 175.4 dB, the best among the reported results for CT-IADCs. It achieves a 5-dB FoMS improvement on the state-of-the-art works.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25~^{\circ }$ </tex-math></inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$ </tex-math></inline-formula>C, and below 0.74 dB over supply variations of ±5%.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$</tex-math> </inline-formula> -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

This article presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$208\times $ </tex-math></inline-formula> oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

A 10-bit 20-Msample/s CMOS pipelined analog-to-digital converter (ADC) is proposed, which is implemented in a 0.6/spl mu/m double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMCs library of 0.6/spl mu/m mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 5MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.