Analysis and Design of a 16-bit Continuous-Time Incremental Delta-Sigma ADC

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

Incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are one of the best candidates for integrated sensor interface systems when it comes to high resolution and power efficiency. Advanced architectures such as Multistage noise shaping (MASH) or extended counting (EC) I-DS ADCs can be used to achieve a high resolution and fast conversion times and avoid stability issues. Different architectures have been proposed in the state of the art (SoA), but there exists no extensive quantitative or qualitative comparison between them. This manuscript fills this gap by providing a detailed system-level comparison between MASH, EC, and other architectural options in I-DS ADCs, where different performances between these architectures are realized depending on the employed oversampling ratio (OSR) and the chosen number of quantizer bits. Also, for specific MASH designs, the appropriate choice of the digital filter improves the SQNR. The advantages, disadvantages, and limitations of the different architectures are presented including non-idealities such as coefficient mismatch showing that 2-1 MASH-LI is less sensitive to mismatch and provides a high maximum stable amplitude (MSA) relative to the simulated architectures. Furthermore, the 2-1 EC achieves good results and comes with the advantage of a lower noise penalty factor compared to the MASH architectures. This work is intended to assist designers in selecting the most appropriate enhanced I-DS MASH architecture for their specific requirements and applications.

Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta–sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma$ </tex-math></inline-formula> ) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2–2 MASH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40° to 125° and within 2-dB SNDR degradation for frequency variations of 20% range.

We propose a hybrid Analog to Digital Converter (ADC) combined with the first-stage as a first-order feedforward incremental (FF I-) ADC and the second-stage as a SAR (Successive Approximation Register) ADC as high-precision and high-speed ADCs. As a result of simulation, the proposed hybrid ADC correctly converts data even if capacitance in FF path of the first-order I-ADC has 10% error.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step.

Continuous-time delta-sigma modulators (CT DSMs) have been widely adopted in IoT and sensor applications. Despite the merits of the inherent anti-alias property and easy-driving resistive input, CT DSMs always suffer from the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> variation issue. While a higher maximum stable amplitude (MSA) can result in a higher dynamic range (DR) with better efficiency, it is often limited to -1 dBFS. To address the above issues, this article presents a hybrid 1-2 sturdy multi-stage noise-shaping (MASH) architecture that exhibits high robustness against <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> variations. The proposed modulator integrates a first-order <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i>-variation-insensitive CT loop filter with a second-order noise-shaping (NS) successive approximation register (SAR) quantizer. By leveraging the inherent unity signal transfer function (STF) of the NS-SAR quantizer, the quantization noise of the first stage is effectively canceled without requiring analog-digital matching. This enables the modulator to achieve a beyond-the-rail MSA while performing aggressive third-order NS. Fabricated in a 55-nm CMOS process, the prototype achieves a measured signal-to-noise-and-distortion ratio (SNDR) of 89.1 dB and a DR of 95.3 dB over a signal bandwidth of 100 kHz, while consuming 459 μW from a single 1.2-V supply. These results yield a state-of-the-art Schreier figure of merit of 178.7 dB among prior art with similar bandwidth. Additionally, the prototype demonstrates robust performance across a wide range of temperatures.

Digitally-assisted integrated circuit design has gained popularity in recent years due to challenges associated with analog components in mixed-signal systems-on-a-chip, which include process variations, mismatches, and increased demand for circuit complexity in sub-micron fabrication process technologies. To optimize efficiency and cost, the focus during hardware design is increasingly directed on the creation of reliable and robust circuits that are immune to variations and unpredictable factors out of the designer's control. On the other hand, the circuits should be power and area efficient to adapt to the needs associated with portable devices, wireless communications, and the global energy and cost saving trends. On-chip calibration techniques can be developed to address these issues by reducing the sensitivity of analog circuit designs, thereby improving their universal usefulness and scalability. Another emerging trend is the rising demand for high-speed low-power analog-to-digital converters (ADCs) to accommodate the increased use of digital processing and big data. The research described in this thesis unites these topics in a design approach for ADCs. This thesis introduces the design of a 3-bit flash ADC with an offset calibration scheme, which is integrated into a two-step 8-bit hybrid flash/successive approximation register (SAR) architecture with time-interleaving. Due to the hybrid architectural structure, the offset requirement for the flash ADC is more stringent than for a conventional standalone 3-bit ADC. Two pairs of transistors are employed to adjust the offsets for each of the seven comparators in the flash ADC by creating a current flow imbalance between the comparator's branches. The amount of current injected in each branch is controlled through the gate voltages of the calibration transistors, which are generated with automatic on-chip calibration circuitry that was developed as part of this research. The circuits were designed, simulated, and fabricated using 130nm complementary metal-oxide semiconductor (CMOS) technology. The calibration path emulates the ADC's normal operation to establish realistic loading and transient effects. Furthermore, the design approach addresses integration challenges within the hybrid ADC system, such as kickback noise and common-mode variations. Monte Carlo simulation results show that the offset standard variation is reduced from 19.2mV to 0.582mV through the calibration. The power consumption of all digital circuits is 1.36mW from a separate 1.2V supply, and the power consumption of the calibration logic with a 10MHz clock is 0.60mW. The dynamic latched comparator of the flash ADC with kickback reduction was evaluated with post-layout simulations including process-voltage-temperature (PVT) variations. It has a 231ps propagation delay, and consumes 0.16mW. From simulations of the flash ADC, the worst-case effective number of bits (ENOB) is 2.88, and the worst-case signal-to-noise-and-distortion ratio (SNDR) is 19.1dB in the slow process corner case with a temperature of 85 degree Celsius and 1.14V supply. The flash ADC consumes 3.6mW. The comparator design incorporates a kickback reduction technique that reduces the kickback effect from 23.3mV to 1.2mV for a 500mV input during system-level simulations. Measurements of a prototype chip show that the ENOB improves from 3.64 to 5.24 bits using a 500MHz clock during automatic calibration.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.