Analysis and Design of RC-Variation-Robust Continuous-Time Delta-Sigma Modulator with Boosted MSA

Continuous-time (CT) delta-sigma modulator (DSM) is a popular choice for its inherent aliasing and resistive input impedance characteristics. With the increased demands for wide-bandwidth (BW) and high-dynamic range (DR), multistage noise shaping (MASH) presents prominent benefits of high-order noise-shaping (NS) without being constrained by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> loop stability issues. Recent literature on CT MASH DSM showed promising progress in overcoming the design challenges under wideband application, including signal and quantization leakage, analog-digital matching complexity, signal transfer function (STF) peaking, and high-speed excess loop delay (ELD) compensation. This review article introduces fundamental models and primary design considerations, then discusses the CT MASH DSM’s key challenges and corresponding solutions. Finally, we provide two implementation examples of this architecture with their highlights and challenges.

Incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are one of the best candidates for integrated sensor interface systems when it comes to high resolution and power efficiency. Advanced architectures such as Multistage noise shaping (MASH) or extended counting (EC) I-DS ADCs can be used to achieve a high resolution and fast conversion times and avoid stability issues. Different architectures have been proposed in the state of the art (SoA), but there exists no extensive quantitative or qualitative comparison between them. This manuscript fills this gap by providing a detailed system-level comparison between MASH, EC, and other architectural options in I-DS ADCs, where different performances between these architectures are realized depending on the employed oversampling ratio (OSR) and the chosen number of quantizer bits. Also, for specific MASH designs, the appropriate choice of the digital filter improves the SQNR. The advantages, disadvantages, and limitations of the different architectures are presented including non-idealities such as coefficient mismatch showing that 2-1 MASH-LI is less sensitive to mismatch and provides a high maximum stable amplitude (MSA) relative to the simulated architectures. Furthermore, the 2-1 EC achieves good results and comes with the advantage of a lower noise penalty factor compared to the MASH architectures. This work is intended to assist designers in selecting the most appropriate enhanced I-DS MASH architecture for their specific requirements and applications.

This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achieving enhanced resolution and improved linearity with little power consumption is possible. Additionally, several energy-efficient techniques are adopted. Fabricated in 55-nm CMOS, the prototype occupies 0.36mm2 active area and consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$188.6\mu $ </tex-math></inline-formula>W from a 1.2-V supply. The implemented CT-IADC achieves a measured dynamic range (DR) of 96.5 dB and a signal-to-noise-and-distortion ratio (SNDR) of 95.4 dB for a maximum input of 1.9Vpp and a bandwidth of 20kHz. The measured SNDR-based Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula>) is 175.4 dB, the best among the reported results for CT-IADCs. It achieves a 5-dB FoMS improvement on the state-of-the-art works.

This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta–sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma$ </tex-math></inline-formula> ) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2–2 MASH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40° to 125° and within 2-dB SNDR degradation for frequency variations of 20% range.

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8.

This paper presents a self-coupled discrete-time multistage noise-shaping (MASH) delta-sigma modulator (DSM) with using an infinite impulse-response (IIR) filter between two stages. By introducing an IIR filter into the self-coupled path, the proposed MASH DSM could compensate the loss of maximum stable amplitude (MSA) owing to the injected self-coupled path. A larger MSA results in a higher power efficiency. Moreover, the IIR filter is implemented as first-order without imposing explicit hardware complexity. The behavioral-level simulations confirm the concept of the proposed MASH DSM.

To meet the demand for high-precision biological signal detection in wearable biomedical devices, this paper proposes the design of a fourth-order discrete-time sigma–delta analog-to-digital converter (ADC) employing a multi-stage noise shaping (MASH) 2-2 architecture. In the first-stage sub-modulator, the first integrator adopts a double-sampling structure, which improves noise shaping performance markedly. A novel common-mode feedback (CMFB) circuit has also been designed, which addresses the phase-dependent loading issue in traditional switched-capacitor networks. Notably, a dynamically activated nonuniform quantization mode is innovatively proposed in the second stage. It integrates 2.5-bit coarse quantization with 2-bit fine quantization in specific intervals, enabling high-precision detection of the small-amplitude quantization errors from the first-stage sub-modulator. In addition, the comparator in this stage integrates feed-forward summation capability and retains input offset voltage storage (IOS) technology to reduce the offset voltage. Meanwhile, the designs of dynamically activated nonuniform quantizer and comparator with integrated summation function have reduced the power consumption of the modulator by 19%. In a 180-nm CMOS process, the modulator occupies a layout area of 0.57[Formula: see text]mm 2 and simulation results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 113.2[Formula: see text]dB. After processing by the cascaded integrator comb (CIC) decimation filter, the ADC achieves a peak SNDR of 115.6[Formula: see text]dB, an effective number of bits (ENOB) of 18.91 bits and a power consumption of 4.36[Formula: see text]mW under a 1.8[Formula: see text]V supply. These performance metrics correspond to a state-of-the-art figure-of-merit (FoM) of 175.1[Formula: see text]dB.

A 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is presented with the dual-capacitor merge-and-split (DCMS) switching scheme for low-power sensing applications. The proposed switching scheme features the constant common-mode voltage, so the dynamic offset can be relaxed obviously. Meanwhile, compared to the conventional switching scheme, the proposed switching scheme achieves 99.22% reduction in average switching energy and 50% capacitor area saving due to only using the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</inf> reference level. Simulation results illustrate that the NS-SAR ADC consumes 6.19 µW when operating at 1-MS/s. It achieves a Schreier FoM of 168.2 dB with 68.13 dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8 and 1 V supply in 180 nm CMOS process.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This paper presents a band-pass noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with a second-order modulator which is comprised of a fully passive switched-capacitor (SC) filter and a gain-boosted dynamic amplifier. It employs the error-feedback (EF) structure in a simple method to implement the complicated noise transfer function (NTF) zeros, which enhances the noise-shaping capability by minimally modifying a standard SAR ADC. Designed in 28 nm CMOS process, the prototype of proposed NS-SAR ADC achieves 76.84 dB signal-to-noise and distortion ratio (SNDR) with the bandwidth between 20 and 40 MHz and the FoMw is only 2.24 fJ/step at the oversampling ratio (OSR) of 5.

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

Typical digital cameras exhibit a limitation regarding the dynamic range of the scene radiance they can capture. High Dynamic Range (HDR) imaging refers to methods and systems that aim to generate images that exhibit higher dynamic range between the lightest and the darkest parts of the an image. A typical approach for generating HDR images is exposure bracketing where multiple frames, each one with a different exposure setting, are captured and combined to a HDR image of the scene. The large number of images that exposure bracketing requires often leads to motion artefacts that limit the visual quality of the resulting HDR image. In this work, we propose a novel approach in HDR imaging that significantly reduces the necessary number of images. In our proposed system, we employ the notion of random exposure where each pixel of a single frame collects light for a random amount of time. By collecting a small number of such images, the full sequence of low dynamic range images can be reconstructed and subsequently used for HDR generation. The problem is solved by casting the reconstruction of the sequence as a nuclear norm minimization problem following the premises of the recently proposed theory of Matrix Completion. Experimental results suggest that the proposed method is able to reconstruct the sequence from as low as 20% of the images that traditional techniques require with minimal reduction in image quality.

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