Preweighted Linearized VCO Analog-to-Digital Converter

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$</tex-math> </inline-formula> -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

A 10-bit 20-Msample/s CMOS pipelined analog-to-digital converter (ADC) is proposed, which is implemented in a 0.6/spl mu/m double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMCs library of 0.6/spl mu/m mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 5MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25~^{\circ }$ </tex-math></inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$ </tex-math></inline-formula>C, and below 0.74 dB over supply variations of ±5%.

This article presents an intrinsically linear continuous-time (CT) zoom analog-to-digital converter (ADC) architecture that uses a coarse first-order CT delta-sigma modulator (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M) followed by a fine third-order CT-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M. The 1.5-bit output of the coarse CT-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M is filtered by an 8-tap finite impulse response (FIR) filter, and then, a current-steering DAC provides intrinsically linear outputs to the fine <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M. The associated delay is mitigated by increasing the coarse sampling rate by a factor of 4. The coarse <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M significantly relaxes the requirements of the fine <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>M, but despite the faster sampling rate, consumes negligible power, because its noise is canceled for the final output, allowing the use of a relatively large input resistor. The ADC prototype fabricated in a 65-nm CMOS process occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.124~{\text {mm}^{{2}}}$ </tex-math></inline-formula> and consumes only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$243~{\mu }$ </tex-math></inline-formula>W from a 1.2-V supply. It achieves 92.0-dB signal-to-noise and distortion ratio (SNDR), 92.3-dB signal-to-noise ratio (SNR), 97.4-dB dynamic range (DR), and 105.7-dB spurious-free DR (SFDR) over a 50-kHz bandwidth without using DAC linearization or calibration. This corresponds to Schreier FoMs of 175.1 dB (SNDR) and 180.5 dB (DR).

This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta–sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma$ </tex-math></inline-formula> ) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2–2 MASH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40° to 125° and within 2-dB SNDR degradation for frequency variations of 20% range.

This paper presents a 10-bit 100MS/s analog to digital converter (ADC) that based on successive approximation (SAR) algorithm. This ASIC is to fulfill the requirement of Hadronic Calorimeter (HCal) upgrade: custom cost-efficient high sampling digitizer electronics and capable of continuous operation mode. The designed chip is developed by using the TSMC 65nm CMOS technology. The post-layout simulations show this ADC could achieve peak signal to noise and distortion ratio (SNDR) of 58 dB at Nyquist rate input frequency and power consumption of 3.5 mW. The peak effective number of bits (ENOB) is 9.6 bits, equivalent to the figure of merit of 45 fJ/conversion step.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents a band-pass noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with a second-order modulator which is comprised of a fully passive switched-capacitor (SC) filter and a gain-boosted dynamic amplifier. It employs the error-feedback (EF) structure in a simple method to implement the complicated noise transfer function (NTF) zeros, which enhances the noise-shaping capability by minimally modifying a standard SAR ADC. Designed in 28 nm CMOS process, the prototype of proposed NS-SAR ADC achieves 76.84 dB signal-to-noise and distortion ratio (SNDR) with the bandwidth between 20 and 40 MHz and the FoMw is only 2.24 fJ/step at the oversampling ratio (OSR) of 5.

A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V} _{\rm PP} $</tex></formula> ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V} _{\rm PP}$</tex></formula> two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.

A 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is presented with the dual-capacitor merge-and-split (DCMS) switching scheme for low-power sensing applications. The proposed switching scheme features the constant common-mode voltage, so the dynamic offset can be relaxed obviously. Meanwhile, compared to the conventional switching scheme, the proposed switching scheme achieves 99.22% reduction in average switching energy and 50% capacitor area saving due to only using the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</inf> reference level. Simulation results illustrate that the NS-SAR ADC consumes 6.19 µW when operating at 1-MS/s. It achieves a Schreier FoM of 168.2 dB with 68.13 dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8 and 1 V supply in 180 nm CMOS process.