A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

In this paper, we present a novel single-path multi-bit delta-sigma analog-to-digital converter (/spl Delta//spl Sigma/ ADC) architecture that uses time as a reference for performing multi-bit digital-to analog conversion in the feedback path. The architecture uses a voltage-controlled oscillator (VCO) as a multi-bit quantizer. In the feedback path of the /spl Delta//spl Sigma/ ADC, the errors due to component mismatch are avoided by using a single-path for all the levels in a multi bit digital to-analog converter (DAC). The technique eliminates the need for feedback DAC architectures with static and dynamic component matching.

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltagecontrolled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling.

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC

A Nyquist voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) architecture is proposed for ac-coupled systems that are commonly used in high-speed wireline and wireless communications. The proposed ADC utilizes a built-in high-pass filter as an analog differentiator, replacing the digital differentiator in conventional oversampling VCO-based ADCs. As a result, it avoids quantization noise shaping and achieves wideband Nyquist operation, inherited first-order antialiasing filtering, and improved VCO linearity without calibration. Analyses and simulations of various circuit nonidealities’ effects on the proposed ADC architecture are also provided. The ADC prototype achieves a peak SNDR of 34 dB and an SFDR of 50 dB with over 400-MHz input bandwidth and a sampling rate of 800 MS/s. It occupies an active area of 0.01 mm2 and consumes 3.62 mW in 65-nm CMOS.

A linearization technique of voltage-to-frequency characteristics of voltage-controlled oscillator (VCO) analog-to-digital converters (ADCs) is presented. In contrast to previous works, the proposed technique is an open-loop calibration-free configuration, so it can operate at higher frequencies. It is also independent of the delay element structure, so it can be applied to various VCO ADC topologies. The analog input signal is first mapped through a preweighted resistor network in which every delay element experiences a different version of the input and produces the corresponding delay. As a result, the proposed approach suppresses the impact of V/F nonlinearity on the ADC performance by expanding a linear region of the transfer curve over the full rail-to-rail input. This technique shows substantial improvement results by keeping nonlinearity within ±0.5% over the full input scale (dBFS) and achieves a peak signal-to-noise and distortion ratio (SNDR) of 75.7 and 60.4 dB for input of -8 and 0 dBFS, respectively.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.

A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.

In this paper, we propose a 12-bit 100-MHz current-steering digital-to-analog converter (DAC) for system-on-a-chip (SOC) applications. We adapt the segmented architecture to design this DAC to obtain better performances of INL, glitch energy, and monotonicity. The segmented architecture includes 7-MSBs which are decoded into 127 equally weighted current sources and 5-LSBs which are corresponding to binary-weighted current sources. Based on the TSMC 0.35/spl mu/m 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL < /spl plusmn/0.4LSB, DNL < /spl plusmn/0.25LSB, and settling time less than 9ns. The proposed converter's spurious free dynamic ranges (SFDRs) for are larger than 80 dB and 65 dB at an update rate (f/sub CLK/) 100MHz and its output frequencies are 1 MHz and 49 MHz, respectively. The power consumption is 47 mW at the maximum conversion rate.

The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage. An exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. This paper is going to review the recent development in time-based noise-shaping ADCs, so-called as time-based sigma-delta modulators. Two of the most important architectures named as voltage-controlled oscillator (VCO) -based and time-to-digital (TDC) -based sigma-delta modulators (SDMs) are selected to be reviewed in this paper. The intrinsic advantages and limitations of the these structures are briefly explored. To confirm the effectiveness of the time-mode sigma-delta modulators, a TDC-based continuous-time sigma-delta modulator is proposed as an example and the related simulation results performed in MATLAB are illustrated. The simulation results show that the proposed modulator achieves a dynamic range of 67 dB over 30 MHz with the loop filter of order 2. The proposed TDC-based sigma-delta modulator shows the superiority of the time quantization approach in designing the wideband and less complex continuous-time SDMs.

China will establish the Xihe System based on Beidou/GNSS, Mobile Communication, Internet and Satellite Communication system to realize the Seamless Outdoor and Indoor Positioning in Wide Area (SOIPWA) on personal mobile terminals. Indoor Positioning System (IPS) is one of the main components and effective supplement for indoor positioning signal resource to resolve the positioning signal coverage of blind areas in complicated indoor environment based on current 2G/3G communication network and existing equipment. According to the requirement, the IPS adopted the unified time-frequency reference which affects the accuracy of indoor positioning directly. This paper provides an acquisition method of high accuracy frequency source used in the indoor positioning signal supplement. Positioning signals from outdoor base stations are acquired by RF front end and tracked by the carrier loop and code loop adjusting. After that, positioning signals are locked and synchronized to extract the high accuracy frequency source used for IPS, which can be built with low cost and precisely integrated with an outdoor positioning system. In practical test, the method satisfies the need of the accuracy and stability in time-frequency reference for IPS with high frequency accuracy, quick start and low drift rate through adjusting high accuracy Voltage Controlled Oscillator (VCO) by Digital to Analog Converter (DAC) with the frequency difference result from the adaptive loop.

This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.