Stochastic ΔΣ VCO-ADC Utilizing 4× Staggered Averaging

Testing high resolution DACs: A contribution to draft standard IEEE P1658

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

**Please read the paper on the following link:** https://ieeexplore.ieee.org/document/9178737 **Abstract:** A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this work. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring-oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of signal-band and also has intrinsic interferer rejection capability. A prototype ADC fabricated in 65nm CMOS is operated at an IF of 52MHz. The ADC has an SNDR of 63.1dB and 59.5dB at 1.04MHz and 4.3MHz bandwidth, respectively. The ADC consumes only 0.36mW power from a 0.9V supply and has an energy efficiency of 21fJ/step improving upon the current state-of-the-art by 3.5x.

This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.

A low-power, small-area, and medium-resolution analog-to-digital converter (ADC) is one of the critical building blocks in a system-on-chip (SoC). But it is also a primary bottleneck of SoC time-to-market due to full custom design. To improve design efficiency, the digital synthesis tools are employed to accelerate its layout design as long as the ADC mostly consists of digital standard cells and can be described in Hardware Description Languages (HDLs). This kind of ADC is called as synthesizable ADC [1–2], in which a voltage-controlled oscillator (VCO)-based ADC has become a popular choice because of its high digitization. However, the open-loop VCO-based ADC suffers from the inherent nonlinearity of VCO and necessitates calibration [3]. A closed loop is adopted to suppress the nonlinearity [4], but requires a feedback scheme with a digital-to-analog converter (DAC). A bi-level feedback scheme in the digital style is proposed in [5], but it ignores the lead-lag status between dual VCO. A tri-level feedback scheme is proposed in [6] to make full use of the phase resolution. However, it is designed in the analog style and hard to synthesize due to analog circuitry, including analog switches and reference generators.

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC's input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC's coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC's fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC's output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

This work presents a 180-nm CMOS bandpass ΣΔ Analog-to-Digital Converter (ADC) developed to fulfill the specifications of a fully-integrated receiver for Magnetic Resonance Imaging (MRI). CMOS integration of a multichannel digital receiver would increase the quality of the image without the need of using many coaxial cables to connect the RF coils (located close to the patient) with the digitizing and processing hardware. A very simple Low-IF receiver is proposed with digital IQ demodulation, where a continuous time Low-IF bandpass ADC is the most efficient architecture. The continuous time circuitry can be used to remove the classical filter, as in this application no interferers are expected, and an anti-alias filter is enough. The bandpass loop filter attenuates the quantization noise in the narrow input bandwidth, while stability is easily achieved, as in many low-pass loop filters, due to the selected Low-IF. Measurements show 82dB DR over 1MHz bandwidth, centered at 5MHz. The measured IMD3 product is 74dB, which is good enough for the application.

In this paper, we study on the automatic gain control (AGC) scheme for pulse amplitude modulation (PAM) with 1.8-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) analog-to-digital converters (ADCs) by TSMC 0.18-um CMOS process. For M-PAM networked control systems, this design investigate the problem of AGC schemes under the assumption that applied ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation are used at the receiver end. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic on robotic wireless control system. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization. For of the fixed threshold ADCs, and altering the gain to ADC input, we propose an algorithm based on ADC output's distribution-function to adjust the gain of the amplifier in front of the ADC.

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

In this paper, we present a novel single-path multi-bit delta-sigma analog-to-digital converter (/spl Delta//spl Sigma/ ADC) architecture that uses time as a reference for performing multi-bit digital-to analog conversion in the feedback path. The architecture uses a voltage-controlled oscillator (VCO) as a multi-bit quantizer. In the feedback path of the /spl Delta//spl Sigma/ ADC, the errors due to component mismatch are avoided by using a single-path for all the levels in a multi bit digital to-analog converter (DAC). The technique eliminates the need for feedback DAC architectures with static and dynamic component matching.

A new digital background calibration technique to compensate the capacitor mismatch in pipelined analog-to-digital converters (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to global gain error. A simple modification to the conventional MDAC allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC. This method does not produce any limitation of the ADC in terms of speed or input dynamic range.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BISTn1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BISTn2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.

To recover the analog voltage at the input of an analog-to-digital converter (ADC) from its digital output, one needs to know at least the ADC gain and offset. For high-accuracy measurements, it is necessary to estimate the actual values of these parameters since they are usually different from the ideal values (one and zero, respectively). This estimation inevitably has an uncertainty, which contributes to the uncertainty of any measurement made with the ADC. Here, the precision of gain and offset error estimators, based on the histogram method for ADC testing is analyzed. The “terminal based” and “independently based” definitions are compared, both through simulation and experimental evaluation. Our conclusion is that, in typical conditions, the “independently based” definition is more precise.

Digital-to-analog converter (DAC) circuit component errors create non-uniform quantization code widths and nonlinear distortion in the DAC's output. In this project, a low complexity 8-bit digital-to-analog converter with partial randomization dynamic element matching (DEM) technique is designed to eliminate pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in high-resolution DACs. The benefit of this technique is that it gives significantly reduced hardware complexity with no reduction in performance. Simulation results show that nonlinear distortion is greatly suppressed with partial randomization DEM, which offers considerable additional reduction in hardware complexity. In conclusion, this study showed another technique which intends to increase the accuracy and spectral purity of the output signal in data converters.