HLC: software-based half-level-cell flash memory

Flash memory is rapidly deployed as data storage for embedded and tablet PCs due to its shock resistance, fast access, and low power consumption. However, it has some intractable characteristics such as erase-before-write, asymmetric read/write/erase speed, and limited number of write/erase cycles. Due to these hardware limitations, the magnetic disk-based systems and applications could hardly make full use of the advantages of flash memory when directly adopting themselves on it. For example, the frequent changes of B-tree can degrade the storage performance of flash memory. Most of the recent studies on flash-aware index design focused mainly on the buffer management scheme whereby they can reduce the costly write operations to flash. However, in this paper, we present a novel B-tree storage scheme, a group round robin based B-tree index storage scheme, which applies a dynamic grouping and round robin techniques for erase-minimized storage of B-tree in flash memory under heavy-update workload. Experiment results show that the proposed scheme is efficient for frequently changed B-tree structure and improves the I/O performance by 2.14X at best, compared to the related work.

Flash memory is a non-volatile storage device that can retain its contents when the power is switched off. Generally, it is a form of an electrically erasable programmable read-only memory (EEPROM) that offers several excellent features such as less noise, solid-state reliability, lower power consumption, smaller size, light weight, and higher shock resistant [1 – 5]. Flash memory acts as a slim and compact storage device. It’s main applications are such as compact flash (CF), secured digital (SD), and personal computer memory card international association (PCMCIA) cards, for storage and data transfer in most portable electronic gadgets such as mobile phones, digital cameras, personal digital assistants (PDAs), portable media players (PMPs), gobal positioning system receivers (GPS), just to name a few.

Flash memory has been widely used in various embedded computing systems and portable devices in recent years because of its small size, shock-resistance, low-power consumption and non-volatile properties. To hide the disadvantages of flash memory such as out-of-place update, a flash translation layer (FTL) is usually used for providing transparent block-device emulation. But when index structures are implemented over FTL, intensive overwrite operations caused by record inserting, deleting, modifying and index reorganizing could not only degrade the performance significantly but also reduce the life of flash memory. To address the problem, BFTL and IBSF are proposed. However, neither of them could avoid the loss of records and incompatibilities when system crash occurs. In this paper, a reliable B-tree implementation called RBFTL is presented for flash-memory storage systems. It is placed between the application layer and FTL. RBFTL could minimize the loss of data and eliminate incompatibilities effectively and efficiently when system crashes. The experimental results also show that RBFTL yields a better performance than FTL.

Flash memory, especially NAND flash memory, is being rapidly deployed as data storage for mobile devices such as mobile phones, digital cameras and PDA's. With its capacity increasing and price dropping, Flash memory has been installed in many portable computers instead of magnetic disk for its light weight, small size, physical stability and low power consumption. We may expect that Flash memory will finally take the place of magnetic disk in the next few years. It is possible for us to consider running a database system on the flash computing platforms. Therefore, this requires an efficient index structure to locate a particular item quickly from a huge amount of database records. However, disk-based database index can not be used on flash memory directly because of different characteristics between flash memory and magnetic disk. In this paper, we propose a logging approach on B+-tree index for flash-based DBMS. This new approach makes use of the characteristics of flash memory effectively to acquire more benefits from using traditional database index technology on flash memory.

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

NAND flash memory has been widely used to build embedded devices such as smartphones and solid state drives (SSD) because of its high performance, low power consumption, great shock resistance and small form factor. However, its lifetime and performance are greatly constrained by partial page updates, which will lead to early depletion of free pages and frequent garbage collections. On the one hand, partial page updates are prevalent as a large portion of I/O does not modify file contents drastically. On the other hand, general-purpose cache usually does not specifically consider and eliminate duplicated contents, despite its popularity.In this paper, we propose a hybrid approach called FTL2, which employs both logging and mapping techniques in flash translation layer (FTL), to tackle the endurance problem and performance degradation caused by partial page updates in flash memory. FTL2 logs the latest contents in a high-speed temporary storage, called Content Cache to handle partial page updates. Experimental results show that FTL2 can greatly reduce page writes and postpone garbage collections with a small overhead.

Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory’s physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory.

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

Flash memory is becoming a major database storage in building embedded systems or portable devices because of its non-volatile, shock-resistant, power-economic nature, and fast access time for read operations. Flash memory, however, should be erased before it can be rewritten and the erase and write operations are very slow as compared to main memory. Due to this drawback, traditional database management schemes are not easy to apply directly to flash memory database for portable devices. Therefore, we improve the traditional schemes and propose a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing in a flash memory database environment. F2PL achieves high transaction performance by exploiting the notion of the Alternative Version Coordination which allows previous version reads and efficiently handles slow write/erase operations in lock management processes. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional schemes.

With the rapid development of computer technology as a whole, the performance requirements of modern computer systems for storage technology are becoming higher and higher. This paper discusses the response to the problems that have arisen with the traditional storage in today's era, that is, the construction principle of the new storage three-dimensional memory (3D NAND) and the future development. Traditional storage in order to enhance the storage space of the plane flash memory, can only be components for shrinking, when shrinking to a certain extent when the flash memory will occur uncontrollable hidden danger, so the invention of 3D NAND. By vertically stacking many layers of memory cells, the storage density per unit area is greatly increased, with high-speed reading and writing, large capacity, low power consumption and other characteristics. Nowadays, 3D NAND is widely used in enterprises, and the industry is hopeful about the long-term prospects of the growing global demand for data generation and storage and the introduction of new technologies. The development of 3D NAND technology provides higher storage density and lower cost for NAND flash memory to meet the growing demand for data storage. This paper provides a systematic summary of existing research on 3D NAND in the hope that it will better enhance the overall technology improvement in the storage industry.

There is no doubt that video-on-demand (VoD) services are very popular these days. However, disk storage is a serious bottleneck limiting the scalability of a VoD server. Disk throughput degrades dramatically due to seek time overhead when the server is called upon to serve a large number of simultaneous video streams. To address the performance problem of disk, buffer cache algorithms that utilize RAM have been proposed. Interval caching is a state-of-the-art caching algorithm for a VoD server. Flash Memory Solid-State Drive (SSD) is a relatively new storage technology. Its excellent random read performance, low power consumption, and sharply dropping cost per gigabyte are opening new opportunities to efficiently use the device for enterprise systems. On the other hand, it has deficiencies such as poor small random write performance and limited number of erase operations. In this paper, we analyze tradeoffs and potential impact that flash memory SSD can have for a VoD server. Performance of various commercially available flash memory SSD models is studied. We find that low-end flash memory SSD provides better performance than the high-end one while costing less than the high-end one when the I/O request size is large, which is typical for a VoD server. Because of the wear problem and asymmetric read/write performance of flash memory SSD, we claim that interval caching cannot be used with it. Instead, we propose using file-level Least Frequently Used (LFU) due to the highly skewed video access pattern of the VoD workload. We compare the performance of interval caching with RAM and file-level LFU with flash memory by simulation experiments. In addition, from the cost-effectiveness analysis of three different storage configurations, we find that flash memory with hard disk drive is the most cost-effective solution compared to DRAM with hard disk drive or hard disk drive only.

In recent years, flash memory has become more widely used due to its advantages, such as fast data access, low power consumption, and high mobility. However, flash memory also has drawbacks that need to be overcome, such as erase-before-write, and the limitations of block deletion. In order to address this issue, the FTL (Flash Translation Layer) has been proposed with useful functionalities like address mapping, garbage collection, and wear-leveling. During the process of using, the data may be lost on power failure in the storage systems. In some systems, the data is very important. Thus recovery of data in the event of the system crash or a sudden power outage is of prime importance. This problem has attracted attention from researchers and many studies have been done. In this paper, we investigate previous studies on data recovery for flash memory from FTL processing solutions to PLR (Power Loss Recovery) solutions that have been proposed by authors in the conference proceeding, patents, or professional journals. This will provide a discussion of the proposed solutions to the data recovery in flash memory as well as an overview.

As the flash memory performance increases with more bandwidth, the flash memory channel or the interconnect is becoming a bigger bottleneck to enable high performance SSD system. However, the bandwidth of the flash memory interconnect is not increasing at the same rate as the flash memory. In addition, current flash memory bus is based on dedicated signaling where separate control signals are used for communication between the flash channel controller and the flash memory chip. In this work, we propose to exploit packetized communication to improve the effective flash memory interconnect bandwidth and propose packetized SSD (pSSD) system architecture. We first show how packetized communication can be exploited and the microarchitectural changes required. We then propose the Omnibus topology for flash memory interconnect to enable a packetized network SSD (pnSSD) among the flash memory – a 2D bus-based organization that maintains a “bus” organization for the interconnect while enabling direct communication between the flash memory chips. The pnSSD architecture enables a new type of garbage collection that we refer to as spatial garbage collection that significantly reduces the interference between I/O requests and garbage collection. Our detailed evaluation of pnSSD shows 82% improvement in I/O latency with no garbage collection (GC) while improving I/O latency by 9.71× when GC occurs in parallel with I/O operation, through spatial garbage collection.

The flash memory becomes a very popular storage device. Recently, it has replaced the traditional hard disc due to its shock - resistance and low power consumption. However, the flash memory architecture has some limitations related to the data management. Data cannot be updated in-place. That is why the flash translation layer (FTL) must be used. Nowadays, the flash memory seems to be the mature enough storage technology to work with databases. Among many database models, the column oriented databases have attracted the attention. This approach indicates the fact that data from the columns are packed together in the memory blocks. In this paper, we propose the Column Flash Translation Layer (CFTL) as an effective tool to store the data of the column oriented database in blocks of the flash memory