3D NAND Based on Conventional Flash Memory Architecture Research and Application Prospects

Flash memory is a non-volatile storage device that can retain its contents when the power is switched off. Generally, it is a form of an electrically erasable programmable read-only memory (EEPROM) that offers several excellent features such as less noise, solid-state reliability, lower power consumption, smaller size, light weight, and higher shock resistant [1 – 5]. Flash memory acts as a slim and compact storage device. It’s main applications are such as compact flash (CF), secured digital (SD), and personal computer memory card international association (PCMCIA) cards, for storage and data transfer in most portable electronic gadgets such as mobile phones, digital cameras, personal digital assistants (PDAs), portable media players (PMPs), gobal positioning system receivers (GPS), just to name a few.

Flash memory, especially NAND flash memory, is being rapidly deployed as data storage for mobile devices such as mobile phones, digital cameras and PDA's. With its capacity increasing and price dropping, Flash memory has been installed in many portable computers instead of magnetic disk for its light weight, small size, physical stability and low power consumption. We may expect that Flash memory will finally take the place of magnetic disk in the next few years. It is possible for us to consider running a database system on the flash computing platforms. Therefore, this requires an efficient index structure to locate a particular item quickly from a huge amount of database records. However, disk-based database index can not be used on flash memory directly because of different characteristics between flash memory and magnetic disk. In this paper, we propose a logging approach on B+-tree index for flash-based DBMS. This new approach makes use of the characteristics of flash memory effectively to acquire more benefits from using traditional database index technology on flash memory.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

In recent years, flash memory has been widely used in embedded systems, portable devices, and high-performance storage products due to its non-volatility, shock resistance, low power consumption, and high performance natures. To reduce the product cost, multi-level-cell flash memory (MLC) has been proposed; compared with the traditional single-level-cell flash memory (SLC) that only stores one bit of data per cell, each MLC cell can store two or more bits of data. Thus MLC can achieve a larger capacity and reduce the cost per unit. However, MLC also suffers from the degradation in both performance and reliability. In this paper, we try to enhance the reliability and reduce the product cost of flash-memory based storage devices from a totally different perspective. We propose a half-level-cell (HLC) management scheme to manage and reuse the worn-out space in solid-state drives (SSDs); through our management scheme, the system can treat two corrupted pages as a normal page without sacrificing performance and reliability. To the best of our knowledge, this is the first research that reclaims free space by reviving the corrupted pages. The experiment results show that the lifetime of SSD can be extended by 48.54% for the trace of general users applications with our proposed HLC management scheme.

There is no doubt that video-on-demand (VoD) services are very popular these days. However, disk storage is a serious bottleneck limiting the scalability of a VoD server. Disk throughput degrades dramatically due to seek time overhead when the server is called upon to serve a large number of simultaneous video streams. To address the performance problem of disk, buffer cache algorithms that utilize RAM have been proposed. Interval caching is a state-of-the-art caching algorithm for a VoD server. Flash Memory Solid-State Drive (SSD) is a relatively new storage technology. Its excellent random read performance, low power consumption, and sharply dropping cost per gigabyte are opening new opportunities to efficiently use the device for enterprise systems. On the other hand, it has deficiencies such as poor small random write performance and limited number of erase operations. In this paper, we analyze tradeoffs and potential impact that flash memory SSD can have for a VoD server. Performance of various commercially available flash memory SSD models is studied. We find that low-end flash memory SSD provides better performance than the high-end one while costing less than the high-end one when the I/O request size is large, which is typical for a VoD server. Because of the wear problem and asymmetric read/write performance of flash memory SSD, we claim that interval caching cannot be used with it. Instead, we propose using file-level Least Frequently Used (LFU) due to the highly skewed video access pattern of the VoD workload. We compare the performance of interval caching with RAM and file-level LFU with flash memory by simulation experiments. In addition, from the cost-effectiveness analysis of three different storage configurations, we find that flash memory with hard disk drive is the most cost-effective solution compared to DRAM with hard disk drive or hard disk drive only.

In recent years, flash memory has become more widely used due to its advantages, such as fast data access, low power consumption, and high mobility. However, flash memory also has drawbacks that need to be overcome, such as erase-before-write, and the limitations of block deletion. In order to address this issue, the FTL (Flash Translation Layer) has been proposed with useful functionalities like address mapping, garbage collection, and wear-leveling. During the process of using, the data may be lost on power failure in the storage systems. In some systems, the data is very important. Thus recovery of data in the event of the system crash or a sudden power outage is of prime importance. This problem has attracted attention from researchers and many studies have been done. In this paper, we investigate previous studies on data recovery for flash memory from FTL processing solutions to PLR (Power Loss Recovery) solutions that have been proposed by authors in the conference proceeding, patents, or professional journals. This will provide a discussion of the proposed solutions to the data recovery in flash memory as well as an overview.

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

In the current area of information explosion, users’ demand for data storage is increasing, and data on the cloud has become the first choice of users and enterprises. Cloud storage facilitates users to backup and share data, effectively reducing users’ storage expenses. As the duplicate data of different users are stored multiple times, leading to a sudden decrease in storage utilization of cloud servers. Data stored in plaintext form can directly remove duplicate data, while cloud servers are semi-trusted and usually need to store data after encryption to protect user privacy. In this paper, we focus on how to achieve secure re-duplication and recover data in ciphertext for different users, and determine whether the indexes of public key searchable encryption and the matching relationship of trapdoor are equal in cipher text to achieve secure de-duplication. For the duplicate file, the data user’s re-encryption key about the file is appended to the ciphertext chain table of the stored copy. The cloud server uses the re-encryption key to generate the specified transformed ciphertext, and the data user decrypts the transformed ciphertext by its private key to recover the file. The proposed scheme is secure and efficient through security analysis and experimental simulation analysis.

High-density storage of gases remains a major technological hurdle for many fields. The U.S. Department of Energy (DOE), for example, reduced their hydrogen storage targets for automotive applications due to the inability of technologies to reach the system-level targets.1 Without significant improvements in hydrogen storage density, hydrogen as a transportation fuel remains unfeasible. In other fields, the low volumetric and gravimetric storage densities of oxygen gas cylinders can be cumbersome or prohibitively expensive for applications like terrestrial and marine breathing apparatus’ or manned space exploration. Emerging technologies such as sorbents and chemical complexes show potential for gas storage. However, the ability to achieve application-specific gas delivery rates and high storage densities, while operating reversibly at ambient temperature, remains elusive.2, 3 In contrast, it may be possible to achieve high gas storage densities and potentially high gas delivery rates using nanocapillaries when used in conjunction with a membrane electrode assembly (MEA). Hoop stress calculations show that the pressure tolerances of cylinders are inversely proportional to the radius. Indeed, glass microcapillaries have already theoretically4 and experimentally5 demonstrated the capacity to achieve DOE hydrogen storage targets at a materials-level. This technology can be further improved by reducing the capillary radius to the nanoscale; however, the capping and pressurization of the gas in micro- or nanocapillaries remains problematic. Presented here is the fabrication of nanocapillary arrays capped by an MEA for highly reversible storage of gases with the potential for high rate pumping and high-density storage. Very high aspect ratio and densely packed nanocapillary arrays are produced through aluminum anodization. The nanocapillary arrays are capped with either a PEM or an alkaline (anion) exchange membrane (AEM) complete with catalyst nanoparticles on either side of the membrane to form an MEA. This MEA is used to provide controllable electrochemical pumping of hydrogen or oxygen gas into and out of the nanocapillaries. The MEA also serves as a high pressure seal. A theoretical discussion of the potential volumetric and gravimetric storage densities of hydrogen and oxygen in nanocapillary arrays will be presented together with experimental results of electrochemical gas compression into lab-scale devices. The evaluation of both commercial catalyst materials and fabricated nanoparticle catalysts (<10 nm) for hydrogen and oxygen pumping will be discussed. In addition, the performance of both PEM and AEM for electrochemical pumping of oxygen will be compared. A discussion of the electrochemistry within nanocapillaries compared to planar MEAs will be given including the charge transport/transfer processes. The potential failure mechanisms and the technical obstacles to the implementation of our electrochemical membrane approach, together with the current state of the technology and overall storage capacities, will be presented. 1. Hydrogen, Fuel Cells and Infrastructure Technologies Program: Multi-Year Research, Development and Demonstration Plan. US Department of Energy, Energy Efficiency and Renewable Energy 2012. 2. Zhou, L., Progress and problems in hydrogen storage methods. Renewable and Sustainable Energy Reviews 2005, 9 (4), 395-408. 3. Pukazhselvan, D.; Kumar, V.; Singh, S., High capacity hydrogen storage: basic aspects, new developments and milestones. Nano Energy 2012, 1 (4), 566-589. 4. Zhevago, N.; Glebov, V., Hydrogen storage in capillary arrays. Energy Conversion and Management 2007, 48 (5), 1554-1559. 5. Zhevago, N.; Denisov, E.; Glebov, V., Experimental investigation of hydrogen storage in capillary arrays. International Journal of Hydrogen Energy 2010, 35 (1), 169-175.

Flash memory is rapidly deployed as data storage for embedded and tablet PCs due to its shock resistance, fast access, and low power consumption. However, it has some intractable characteristics such as erase-before-write, asymmetric read/write/erase speed, and limited number of write/erase cycles. Due to these hardware limitations, the magnetic disk-based systems and applications could hardly make full use of the advantages of flash memory when directly adopting themselves on it. For example, the frequent changes of B-tree can degrade the storage performance of flash memory. Most of the recent studies on flash-aware index design focused mainly on the buffer management scheme whereby they can reduce the costly write operations to flash. However, in this paper, we present a novel B-tree storage scheme, a group round robin based B-tree index storage scheme, which applies a dynamic grouping and round robin techniques for erase-minimized storage of B-tree in flash memory under heavy-update workload. Experiment results show that the proposed scheme is efficient for frequently changed B-tree structure and improves the I/O performance by 2.14X at best, compared to the related work.

The flash memory becomes a very popular storage device. Recently, it has replaced the traditional hard disc due to its shock - resistance and low power consumption. However, the flash memory architecture has some limitations related to the data management. Data cannot be updated in-place. That is why the flash translation layer (FTL) must be used. Nowadays, the flash memory seems to be the mature enough storage technology to work with databases. Among many database models, the column oriented databases have attracted the attention. This approach indicates the fact that data from the columns are packed together in the memory blocks. In this paper, we propose the Column Flash Translation Layer (CFTL) as an effective tool to store the data of the column oriented database in blocks of the flash memory

Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory’s physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

Flash memory is hugely been using for small handheld to large enterprise applications due to its attractive characteristics like fast access speed, shock resistance and others. Performance oriented applications like multimedia, robotics, OLTP and further require fault tolerant more reliable high throughput. Therefore, flash memory with its remarkable features is an outstanding choice to meet their business needs. In this paper, we propose a firmware/driver based data storage framework to implement RAID 0 on flash memory platform to support the increasing requirements of data reliability and system performance. In our knowledge, this is the first research presented in concerned area. The real time experimental results prove the effectiveness of our technique.