Data storage framework on flash memory based SSD RAID 0 for performance oriented applications

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

With the rapid development of computer technology as a whole, the performance requirements of modern computer systems for storage technology are becoming higher and higher. This paper discusses the response to the problems that have arisen with the traditional storage in today's era, that is, the construction principle of the new storage three-dimensional memory (3D NAND) and the future development. Traditional storage in order to enhance the storage space of the plane flash memory, can only be components for shrinking, when shrinking to a certain extent when the flash memory will occur uncontrollable hidden danger, so the invention of 3D NAND. By vertically stacking many layers of memory cells, the storage density per unit area is greatly increased, with high-speed reading and writing, large capacity, low power consumption and other characteristics. Nowadays, 3D NAND is widely used in enterprises, and the industry is hopeful about the long-term prospects of the growing global demand for data generation and storage and the introduction of new technologies. The development of 3D NAND technology provides higher storage density and lower cost for NAND flash memory to meet the growing demand for data storage. This paper provides a systematic summary of existing research on 3D NAND in the hope that it will better enhance the overall technology improvement in the storage industry.

Continuous improvement in hardware design and advances in wireless communication have enabled the deployment of various wireless sensor applications. Though, sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Flash memory has become a more widespread storage medium for modern wireless devices because of its effective features like nonvolatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Even though flash memory offers many advantages, its special hardware read, write and erase characteristics impose design challenges on storage systems. This survey analysis the flash based storage management techniques proposed for resource constraint sensor devices, in terms of data life, device life, energy, and storage efficiency. Comprehensive simulation results show gradually improved performance in area of wireless sensor networks.

In recent years, flash memory has been widely used in embedded systems, portable devices, and high-performance storage products due to its non-volatility, shock resistance, low power consumption, and high performance natures. To reduce the product cost, multi-level-cell flash memory (MLC) has been proposed; compared with the traditional single-level-cell flash memory (SLC) that only stores one bit of data per cell, each MLC cell can store two or more bits of data. Thus MLC can achieve a larger capacity and reduce the cost per unit. However, MLC also suffers from the degradation in both performance and reliability. In this paper, we try to enhance the reliability and reduce the product cost of flash-memory based storage devices from a totally different perspective. We propose a half-level-cell (HLC) management scheme to manage and reuse the worn-out space in solid-state drives (SSDs); through our management scheme, the system can treat two corrupted pages as a normal page without sacrificing performance and reliability. To the best of our knowledge, this is the first research that reclaims free space by reviving the corrupted pages. The experiment results show that the lifetime of SSD can be extended by 48.54% for the trace of general users applications with our proposed HLC management scheme.

Flash memory is rapidly deployed as data storage for embedded and tablet PCs due to its shock resistance, fast access, and low power consumption. However, it has some intractable characteristics such as erase-before-write, asymmetric read/write/erase speed, and limited number of write/erase cycles. Due to these hardware limitations, the magnetic disk-based systems and applications could hardly make full use of the advantages of flash memory when directly adopting themselves on it. For example, the frequent changes of B-tree can degrade the storage performance of flash memory. Most of the recent studies on flash-aware index design focused mainly on the buffer management scheme whereby they can reduce the costly write operations to flash. However, in this paper, we present a novel B-tree storage scheme, a group round robin based B-tree index storage scheme, which applies a dynamic grouping and round robin techniques for erase-minimized storage of B-tree in flash memory under heavy-update workload. Experiment results show that the proposed scheme is efficient for frequently changed B-tree structure and improves the I/O performance by 2.14X at best, compared to the related work.

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

The advantages of using a commercial-grade component in military systems are cost and availability. This perception, coupled with the idea that commercial components adequately meet the quality and reliability requirements of the military systems marketplace, tempts the military system designer to utilize commercial components. The disadvantages of this practice far outweigh the advantages. This paper discusses these disadvantages by comparing the device performance of commercial grade components and of those adapted for the military systems marketplace. A comparison of cost, availability, and quality is discussed in great detail. Using flash memory as a vehicle, data will be presented, which compares commercial flash memories and adapted flash memories. Adapted flash memories are commercial flash memory components specially configured and screened for military operating environments. This supports the commercial-of-the-shelf (COTS) trends in the military marketplace. Data will be presented showing specific examples of the improvements and the device performance gained when using adapted flash memories. Characteristics of these devices include device optimization at temperature extremes, and implementations of innovative test techniques.

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

Life cycle cost containment of the strategic weapons system (SWS), without loss of ultra high performance, is a very important goal of the entire Navy Strategic Systems Program community. Boeing is responding by guiding large advances in the state-of-the art of fiber optic gyro technology and developing a new associated navigation system. All of the very stringent strategic weapons system (SWS) performance, reliability, and maintainability requirements continue to be exceeded by the electrostatically supported gyro navigator (ESGN). The electrostatically supported gyro (ESG), in production for over 25 years, is the most critical and costly component of the current inertial navigation system. ESGs, however, are extremely expensive to manufacture and repair. Furthermore, the system-level electronic components are difficult to replace because they are rapidly becoming obsolete. The current initiative is focused on containing total ownership costs, especially maintenance costs, without any relaxation of performance, reliability, or maintainability requirements. The key element of this initiative is new gyro technology based on rapidly improving precision IFOG performance, along with cost reduction of fiber and manufacturing processes. This paper discusses the challenges and the approach currently being taken to further the development of high precision interferometric fiber optic gyro (IFOG) technology and its associated inertial navigation system for application to the SSBN.

A great deal of research has been done on solid-state storage media such as flash memory and non-volatile memory in the past few years. While NAND-type flash memory is now considered a top alternative to magnetic disk drives, different types of non-volatile memory have also begun to appear in the market recently. Although some advocates of storage class memory (SCM) predicted that flash memory would give way to SCM in the very near future, we believe that they will co-exist, complementing each other, for a while until the hurdles in its manufacturing process are lifted and storage class memory becomes commercially competitive in both capacity and price. This demo presents an improved design of In-Page Logging (IPL) by augmenting it with Phase Change RAM (PCRAM) in its log area. IPL is a buffer and storage management strategy that has been proposed for flash memory database systems. Due to the byte-addressability of PCRAM and its faster speed for small reads and writes, the IPL scheme with PCRAM can improve the performance of flash memory database systems even further by storing frequent log records in PCRAM instead of flash memory. We report a few advantages of this new design that will make IPL more suitable for flash memory database systems.

FLASH is called flash memory, also known as highperformance non-volatile memory. It combines the advantages of RAM and ROM which can transfer data quickly and maintain data for a long time in case of power failure. This is why many portable digital devices select flash memory as a storage medium. In recent years, the role of flash memory in the embedded field has become increasingly important. In view of the existing problems of FLASH, including slow erasing, difficult data tracking, complicated operation commands and timing, this paper proposes a method of realizing analog SPI + FLASH system based on FPGA which takes advantage of the parallelism, reconfiguration, high real-time and fast speed. In this paper, the DE10 development board of ALTERA company is used to simulate MX25L3206E chip (SPI+FLASH system) with Verilog Hardware Description Language and finite-state machine on QuartusII development platform. Thus, an integrated system platform based on FPGA simulation SPI+FLASH and controller is established, which replaces the function of actual SPI+FLASH. The main work includes decoding operation commands and accurately controlling FLASH work, designing interface timing and control logic, and data transmission with dual-port RAM. Then STM32 is used to simulate the host MCU to send data and instructions to the FLASH system simulated by the FPGA through the SPI interface. Finally, the real-time signal is captured and displayed by using the tool software of Signal TapII Logic Analyzer to achieve the purpose of the system function test.

Flash memory has become a ubiquitous solid-state memory device widely used in portable digital devices, computers and enterprise applications. The development of the information age has demanded improvements in memory speed and retention performance. Here we demonstrate an ultrafast non-volatile flash memory based on MoS2/hBN/multilayer graphene van der Waals heterostructures, which achieves an ultrafast writing/erasing speed of 20 ns through two-triangle-barrier modified Fowler-Nordheim tunnelling. Using detailed theoretical analysis and experimental verification, we postulate that a suitable barrier height, gate coupling ratio and clean interface are the main reasons for the breakthrough writing/erasing speed of our flash memory devices. Because of its non-volatility this ultrafast flash memory could provide the foundation for the next generation of high-speed non-volatile memory.

Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory’s physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory.

In this paper, the key reliability characteristics of the 3D NAND technology are discussed and compared to the 2D NAND corresponding features. It is shown that 3D NAND can achieve up to 50% improvement of the intrinsic cell threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) distribution width, due to increased cell size and between - cell distance. Two 3D NAND specific reliability aspects are discussed in detail. The presence of the polysilicon channel in 3D NAND array causes temperature related cell current and threshold voltage variations. Also, the CMOS Under the Array (CuA) architecture requires the introduction of the GIDL - Assisted Erase technique, which must be properly designed and optimized not to impact the array reliability performance.

This article is aimed at studying the design and implementation of a football player training management system based on smart images. Based on the analysis of the importance of informatization for scientific football training, system performance requirements and intelligent image detection technology, the football player training management is designed. The overall architecture of the system, and the detailed design of each functional module of the system. It mainly includes football player information management module, football player training plan viewing module, training goal formulation module and training information feedback module. The realization of the training management system relies on intelligent image technology to detect and track athletes. Finally, the performance of the system was tested. The test results show that the expected response time of each module of the system when different numbers of users are accessed is within 3 seconds. The longest actual time is 2.64 s, and the actual shortest time is 1.18 s. It can be seen that the response time of the system meets the demand. At the same time, the system throughput rate meets the requirements of this article, and the user pass rate is also above 95%, indicating that the performance of the football player training management system designed in this article is better.