Ultrafast non-volatile flash memory based on van der Waals heterostructures.

The pursuit of non-volatile memory with program speeds below one nanosecond, beyond the capabilities of non-volatile flash and high-speed volatile static random-access memory, remains a longstanding challenge in the field of memory technology1. Utilizing fundamental physics innovation enabled by advanced materials, series of emerging memories2, 3, 4–5 are being developed to overcome the speed bottleneck of non-volatile memory. As the most extensively applied non-volatile memory, the speed of flash is limited by the low efficiency of the electric-field-assisted program, with reported speeds6, 7, 8, 9–10 much slower than sub-one nanosecond. Here we report a two-dimensional Dirac graphene-channel flash memory based on a two-dimensional-enhanced hot-carrier-injection mechanism, supporting both electron and hole injection. The Dirac channel flash shows a program speed of 400 picoseconds, non-volatile storage and robust endurance over 5.5 × 106 cycles. Our results confirm that the thin-body channel can optimize the horizontal electric-field (Ey) distribution, and the improved Ey-assisted program efficiency increases the injection current to 60.4 pA μm−1 at |VDS| = 3.7 V. We also find that the two-dimensional semiconductor tungsten diselenide has two-dimensional-enhanced hot-hole injection, but with different injection behaviour. This work demonstrates that the speed of non-volatile flash memory can exceed that of the fastest volatile static random-access memory with the same channel length.

Non-volatile memories (NVM) including flash memories and resistive memories have attracted significant interest as data storage media. Flash memories are widely employed in mobile devices and solid-state drives (SSD). Resistive memories are promising as storage class memory and embedded memory applications. Data reliability is the fundamental requirement of NVM as data storage media. However, modern nano-scale NVM suffers from challenges of inter-cell interference (ICI), charge leakage, and write endurance, which threaten the reliability of stored data. In order to cope with these adverse effects, advanced coding techniques including soft decision decoding have been investigated actively. However, current coding techniques do not capture the physical properties of NVM well, so the improvement of data reliability is limited. Although soft decision decoding improves the data reliability by using soft decision values, it degrades read speed performance due to multiple read operations needed to obtain soft decision values. In this dissertation, we explore coding schemes that use side information corresponding to the physical phenomena to improve the data reliability significantly. The side information is obtained before writing data into memory and incorporated during the encoding stage. Hence, the proposed coding schemes maintain the read speed whereas the write speed performance would be degraded. It is a big advantage from the perspective of speed performance since the read speed is more critical than the write speed in many memory applications. First, this dissertation investigates the coding techniques for memory with stuckat defects. The idea of coding techniques for memory with stuck-at defects is employed to handle critical problems of flash memories and resistive memories. For 2D planar flash memories, we propose a coding scheme that combats the ICI, which is a primary challenge of 2D planar flash memories. Also, we propose a coding scheme that reduces the effect of fast detrapping, a degradation factor in 3D vertical flash memories. Finally, we investigate the coding techniques that improve write endurance and power consumption of resistive memories.

The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change random-access memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

As the power dissipation has become one of the critical design challenges in a sensor network environment, non- volatile memories such as STT-MRAM and flash memory will be used in the next generation sensor nodes. In this paper, we studied an efficient buffer management scheme considering the write limitation of STT-MRAM based main memory as well as the erase-before-write limitation of flash memory for storage device. The goal of proposed scheme is to minimize the number of write operations on STT- MRAM as well as the number of erase operations on flash memory. We showed through simulation that proposed scheme outperforms legacy buffer management schemes. Index Terms - Non-volatile memories, Low power, Buffer management, STT-MRAM, NAND flash memory.

Flash memory, especially NAND flash memory, is being rapidly deployed as data storage for mobile devices such as mobile phones, digital cameras and PDA's. With its capacity increasing and price dropping, Flash memory has been installed in many portable computers instead of magnetic disk for its light weight, small size, physical stability and low power consumption. We may expect that Flash memory will finally take the place of magnetic disk in the next few years. It is possible for us to consider running a database system on the flash computing platforms. Therefore, this requires an efficient index structure to locate a particular item quickly from a huge amount of database records. However, disk-based database index can not be used on flash memory directly because of different characteristics between flash memory and magnetic disk. In this paper, we propose a logging approach on B+-tree index for flash-based DBMS. This new approach makes use of the characteristics of flash memory effectively to acquire more benefits from using traditional database index technology on flash memory.

Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

This session will discuss papers related to nanoscale poly floating-gate and charge trap non-volatile memories. The first two papers are on poly-floating gate technologies, the next three are on charge-trap flash memories and the last two are on 3-D NAND flash memories. In the first paper, Toshiba Corporation reports a floating-gate multi-level NAND flash memory technology scalable to 30nm and beyond technology nodes. In the second paper, Qimonda and the Technical University of Munich present a stochastic model of the program operation in scaled NAND flash memories for investigating the interactions between the memory cell and the memory system. Charge-Trap Flash: The next paper by Numonyx and Politecnico di Milano investigates the Random Telegraph Noise scaling trend for both NAND and NOR flash memories. The fourth paper by Toshiba Corporation presents the scalability of a bulk planar SONOS flash memory with double-tunnel junctions down to 10nm gate length. The next paper by National Tsing Hua and Chiao-Tung University reports a new charge-trap engineered non-volatile memory device with very good memory window and high-temperature data retention. 3-D SONOS Flash: In the fifth paper, Schiltron Corporation presents a novel 3-D stackable high-density flash technology, which combines the smallest TFTs to date in series with strings up to 64 cells in a unique architecture to effectively remove pass disturbs. The last paper by Toshiba Corporation, demonstrates a four NAND string 3-D bit cost scalable flash memory with improved program, erase and disturb operation.

A great deal of research has been done on solid-state storage media such as flash memory and non-volatile memory in the past few years. While NAND-type flash memory is now considered a top alternative to magnetic disk drives, different types of non-volatile memory have also begun to appear in the market recently. Although some advocates of storage class memory (SCM) predicted that flash memory would give way to SCM in the very near future, we believe that they will co-exist, complementing each other, for a while until the hurdles in its manufacturing process are lifted and storage class memory becomes commercially competitive in both capacity and price. This demo presents an improved design of In-Page Logging (IPL) by augmenting it with Phase Change RAM (PCRAM) in its log area. IPL is a buffer and storage management strategy that has been proposed for flash memory database systems. Due to the byte-addressability of PCRAM and its faster speed for small reads and writes, the IPL scheme with PCRAM can improve the performance of flash memory database systems even further by storing frequent log records in PCRAM instead of flash memory. We report a few advantages of this new design that will make IPL more suitable for flash memory database systems.

In the past decade parallel disk systems have been highly scalable and able to alleviate the problem of disk I/O bottleneck, thereby being widely used to support a wide range of data-intensive applications. Optimizing energy consumption in parallel disk systems has strong impacts on the cost of backup power-generation and cooling equipment, because a significant fraction of the operation cost of data centres is incurred by energy consumption and cooling. Although flash memory is very energy- efficient compared to disk drives, flash memory is too expensive to use as a major component in large-scale storage systems. In other words, it is not a cost-effective way to make use of large flash memory to build energy-efficient storage systems. To address this problem, in this paper we proposed a hybrid disk architecture or HYBUD that integrates a non-volatile flash memory with buffer disks to build cost-effective and energy-efficient parallel disk systems. While the most popular data sets are cached in flash memory, the second most popular data sets can be stored and retrieved from buffer disks. HYBUD is energy efficient because flash memory coupled with buffer disks can serve a majority of incoming disk requests, thereby keeping a large number of other data disks in the low-power state for longer period times. Furthermore, HYBUD is cost-effective by the virtue of inexpensive buffer disks assisting flash memory to cache a huge amount of popular data. Experimental results demonstratively show that compared with two existing non-hybrid architectures, HYBUD provides significant energy savings for parallel disk systems in a very cost effective way. Keywords-hybrid parallel disk systems; flash drives; buffer disks; energy conservation; I/O performance

Flash memories are most popular nonvolatile, low cost and high density memories. However, one of problems in the flash memory is large consuming energy for writing the data. Then, we proposed a novel coding algorithm for reduction of the consuming energy and confirmed the effect of the algorithm with the numerical simulations.

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Two-dimensional semiconductors, such as transition-metal dichalcogenides (TMDs) and black phosphorous (BP), have found various potential applications in electronic and opto-electronic devices. However, several problems including low carrier mobility and low photoluminescence efficiencies still limit the performance of these devices. Interfacing 2D semiconductors with functional oxides provides a way to address the problems by overcoming the intrinsic limitations of 2D semiconductors and offering them multiple functionalities with various mechanisms. In this review, we first focus on the physical effects of various types of functional oxides on 2D semiconductors, mostly on MoS2 and BP as they are the intensively studied 2D semiconductors. Insulating, semiconducting, conventional piezoelectric, strongly correlated, and magnetic oxides are discussed. Then we introduce the applications of these 2D semiconductors/functional oxides systems in field-effect devices, nonvolatile memory, and photosensing. Finally, we discuss the perspectives and challenges within this research field. Our review provides a comprehensive understanding of 2D semiconductors/functional oxide heterostructures, and could inspire novel ideas in interface engineering to improve the performance of 2D semiconductor devices.

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

Flash memories are the most widely used type of non-volatile electronic memories. Every flash memory cell has q discrete levels for storing information. A prominent property of flash memories is that although it is easy to increase a cell level, to decrease any cell level, a whole block of cells have to be erased and reprogrammed. To minimize the number of expensive block erasure operations and to maintain the data integrity, the data needs to be stored with a strong error-correcting code that can correct enough errors between two erasure operations. In this paper, we introduce the concept of error scrubbing codes. With this new type of error-correcting codes, the cell levels are actively increased when errors appear, even if the errors increase cell levels as well. We show that error-scrubbing codes can outperform conventional error-correcting codes for multi-level flash memories. We present two families of codes based on the L 1 metric and a modular construction.

This article consists of a collection of slides from the author's conference presentation of a seminar discussing the development and market demand for nonvolatile memory (NVM). Some of the specific topics discussed include: market and demand analyses for NVM technologies; systems that support NVM and applications supported; how flash memories will penetrate the PC markets; and what are the major challenges in the future for these products.