HpFX: A Parallel Orchestration Framework for Indicator-Based Forex Simulations

To date, large-scale fluid simulation with more details employing the Smooth Particle Hydrodynamics (SPH) method or its variants is ubiquitous in computer graphics and digital entertainment applications. Higher accuracy and faster speed are two key criteria evaluating possible improvement of the underlying algorithms within any available framework. Such requirements give rise to high-fidelity simulation with more particles and higher particle density that will unavoidably increase computational cost significantly. In this paper, we develop a new general GPGPU acceleration framework for SPH-centric simulations founded upon a novel neighbor traversal algorithm. Our novel parallel framework integrates several advanced characteristics of GPGPU architecture (e.g., shared memory and register memory). Additionally, we have designed a reasonable task assignment strategy, which makes sure that all the threads from the same CTA belong to the same cell of the grid. With this organization, big bunches of continuous neighboring data can be loaded to the shared memory of a CTA and used by all its threads. Our method has thus low global-memory bandwidth consumption. We have integrated our method into both WCSPH and PCISPH, that are two improved variants in recent years, and demonstrated its performance with several scenarios involving multiple-fluid interaction, dam break, and elastic solid. Through comprehensive tests validated in practice, our work can exhibit up to 2.18x speedup when compared with other state-of-the-art parallel frameworks.

Parallel discrete event simulation frameworks have been widely used to analyze the performance of traditional applications under different scenarios. The existing frameworks are designed to work on a cluster and cloud-based computing environments. With the current advances in the Internet of Things, there is a strong need to revamp such traditional frameworks and make use of the smart connected-devices as an underlying infrastructure to perform simulations. In this article, we propose a new simulation framework, which has been specifically designed to work with diverse heterogeneous devices. The framework allows these heterogeneous mobile devices to participate in a distributed simulation while managing network latency, using device profiles that are maintained by the simulation framework. Moreover, in the proposed framework, random and context-aware simulation task distributions have been explored to manage the devices’ sporadic connectivity. Evaluation results using the well-known PHOLD benchmark demonstrate a gain in the overall efficiency of the proposed simulation system.

Hardware description language (HDL) simulation is the fundamental means of IC verification. The complexity of modern VLSI is constantly posing serious challenges to HDL simulators. We developed a parallel HDL simulation framework in which Verilog HDL is translated into a multithreaded program for parallel execution on an ×86 multi-core processor by following a conservative parallel simulation protocol. We identified two essential problems, deterministic initialization and concurrent memory simulation, which are critical to robust logic simulation. Efficient solutions based on theoretic analysis are proposed to address the problems. Experimental results prove the effectiveness of our simulation framework.

: C++ library classes for Force Structure Simulation (FSS) based on the parallel simulation framework called SPEEDES (Synchronous Parallel Environment for Emulation and Discrete-Event Simulation) was developed. These classes derive from and/or utilize the SPEEDES Application Programming Interface (API), and the SPEEDES simulation methodology for execution on high-performance multiprocessor systems. These FSS classes were designed to be the foundation of a R&D simulation framework for researching predictive course of action analysis. The software will prove an easily extensional means to accommodate an increasingly detailed, powerful and elaborate assessment tool.

The advent of General Purpose Graphics Processing Units (GPGPUs) has spawned a lot of interest in computing high resolution flows in a shorter span of time. In combination with existing parallel programming techniques such as MPI or openMP, one is able to obtain at least one order increase in speed-up for CFD applications on stationary grids. Due to a high throughput/cost ratio, GPUs are increasingly becoming popular among the CFD community. Flow fields on helicopter systems rank among one of the most challenging, and hence are computationally demanding to simulate. Further, presence of multiple bodies moving relative to each other require use of overset grid systems, which in turn, require efficient overset grid assembly methods to support the flow solution. In this context, a computational framework for flow simulation across multiple CPU cores and multiple GPUs has been developed and tested. It is shown that the overall wall-clock time for the simulation can be considerably reduced by using multiple GPU cards. The parallel GPU framework is initially tested using both explicit and implicit schemes for the flow past a sphere. Further, a two-blade hovering rotor test case adopted from literature is used to demonstrate the capability of the code towards simulating rotorcraft flows in a short span of time.

Article Free Access Share on Parallel simulation of TCP/IP using TeD Authors: Brian J. Premore Department of Computer Science, 6211 Sudikoff Laboratory, Dartmouth College, Hanover, New Hampshire Department of Computer Science, 6211 Sudikoff Laboratory, Dartmouth College, Hanover, New HampshireView Profile , David M. Nicol Department of Computer Science, 6211 Sudikoff Laboratory, Dartmouth College, Hanover, New Hampshire Department of Computer Science, 6211 Sudikoff Laboratory, Dartmouth College, Hanover, New HampshireView Profile Authors Info & Claims WSC '97: Proceedings of the 29th conference on Winter simulationDecember 1997 Pages 437–443https://doi.org/10.1145/268437.268522Online:01 December 1997Publication History 8citation161DownloadsMetricsTotal Citations8Total Downloads161Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A parallel computational framework to solve flow and transport in integrated surface–subsurface hydrologic systems

Current earth system models have a large range of uncertainty, owing to differences in the simulation of feedbacks and insufficient information to constrain model parameters. Parameter disturbance experiment provides a straightforward method to quantify the variation uncertainty outputs caused by model inputs. Owing to the software complexity and computational intensity of earth system models, a large-scale simulation framework is needed to support ensemble simulation required by parameter disturbance experiment. This paper presents a parallel framework for the community land model ensemble simulation. After a software structure review of the community land model simulation, a single factor parameter disturbance experiment of a reference computational experiment design is used to demonstrate the software design principles, computational characteristics of individual application, parallel ensemble simulation implementation, as well as the weak scalability of this simulation framework on a high-end computer. Finally, the paper discusses some preliminary diagnostic analysis results of the single factor parameter disturbance experiments. The framework design considerations and implementation details described in this paper can be beneficial to many other research programmes involving large scale, legacy modelling system.

Manifold is a parallel simulation framework for multi-core systems. For full-system simulation, Manifold adopts the timing-directed simulation paradigm that separates the simulation into a functional front-end and a timing back-end. Components in the front-end perform functional simulation of the co

In recent years, transaction level modeling (TLM) has enabled designers to simulate complex embedded systems and SoCs, orders of magnitude faster than simulation at the RTL. The increasing complexity of the systems on one hand, and availability of low cost parallel processing resources on the other hand have motivated the development of parallel simulation environments for TLMs. The existing simulation environments used for parallel simulation of TLMs are intended for general discrete event models and do not take advantage of the specific properties of TLMs. The fine-grain synchronization and communication between simulators in these environments can become a major impediment to the efficiency of the simulation environment. In this work, we exploit the properties of temporally decoupled TLMs to increase the efficiency of parallel simulation. Our approach does not require a special simulation kernel. We have implemented a parallel TLM simulation framework based on the publicly available OSCI SystemC simulator. The framework is based on the communication interfaces proposed in the recent OSCI TLM 2 standard. Our experimental results show the reduced synchronization overhead and improved simulation performance.

Software design for a highly parallel molecular dynamics simulation framework in chemical engineering

Currently, the field of motion control for quadruped robots still faces numerous challenges. One approach to addressing these challenges is the use of deep reinforcement learning techniques, which involve the design of robust reinforcement learning algorithms capable of handling uncertain sensor inputs. These algorithms optimize and execute motion control in dynamic and unpredictable environments, thus enabling legged robots to perform more complex and difficult tasks. In this study, we propose a method for training a robot control policy using deep reinforcement learning. Specifically, we model the control policy as a Multi-Layer Perceptron (MLP) and train it within a simulation environment. To improve the policy’s adaptability to noisy sensor inputs, we implement domain randomization for each sensor input. By leveraging a parallel simulation framework and implementing a high-performance reinforcement learning algorithm, we successfully developed a policy that can accurately track velocity commands, including those significantly higher than those encountered during training, within just one hour. Furthermore, our method demonstrates the ability to guide the robot into specified gaits, such as trotting, by incorporating gait-specific reward functions during the training process.

Parallel simulation has the potential to accelerate the execution of simulation applications. However developing a parallel discrete-event simulation from scratch requires an in-depth knowledge of the mapping process from the physical model to the simulation model, and a substantial effort in optimising performance. This paper presents an overview of the SPaDES (Structured Parallel Discrete-Event Simulation) parallel simulation framework. We focus on the performance analysis of SPaDES/C++, an implementation of SPaDES on a distributed-memory Fujitsu AP3000 parallel computer. SPaDES/C++ hides the underlying complex parallel simulation synchronization and parallel programming details from the simulationist. Our empirical results show that the SPaDES framework can deliver good speedup if the process granularity is properly optimised.

The number of design decisions for communication network hardware in message passing distributed memory systems is quite large, as illustrated by many different implemented and proposed designs. Many of the decisions are driven by, on one side, performance requirements of targeted applications for the parallel system, and on the other side, hardware implementation costs. To obtain cost effective communication hardware matching a certain application domain, use of a parallel architecture simulation framework is inevitable. The simulator presented here, named PARSE, offers a base for such a framework. It can accurately simulate a wide range of communication architectures and, unlike analytic communication models, does properly model all performance aspects. Changing parameters of simulated architectures is very flexible and the object oriented implementation of the simulator facilitates future extensions and enhancements. >

The rapid adoption of heterogeneous multicluster architectures in modern Systems-on-Chip (SoCs) has increased the need for scalable and accurate simulation tools. GEM5 continues to be widely used across academia and industry for microarchitectural exploration, yet its single-threaded event loop limits simulation throughput when evaluating SoCs composed of many interacting CPU clusters, GPUs, NPUs, and memory subsystems. To overcome this bottleneck, we propose PGSI (Parallel GEM5-based Simulation Infrastructure), a parallel simulation framework designed to extend GEM5 while preserving cycle-accurate fidelity. PGSI introduces cluster-level parallelism, a deterministic global synchronization barrier, a lock-free shared-memory emulation layer, and a cycle-accurate Network-on-Chip (NoC) timing model. Across PARSEC, SPEC CPU2017, MobileNet inference, and Android micro-services, PGSI achieves an average 3.4× speed-up over baseline GEM5 while maintaining <2% deviation in IPC, memory latency, and end-to-end execution time. PGSI demonstrates that cycle-accurate simulation of large heterogeneous SoCs can be parallelized effectively without rollback or hardware-assisted execution, providing a practical foundation for future architectural research.