Hybrid Communication Reconfigurable Network on Chip for MPSoC

Network on Chips (NoC) have emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. The use of 3D IC technology in NoC promises to improve communication latency and power. Most of the 3D ICs use Through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 2-layer 3D Butterfly Fat Tree (BFT) variants. Floorplan driven wire and TSV lengths are used to obtained power and performance optimal 3D NoC architectures. We analysed the performance of the output flow control using random and round robin output based deflection routing for 3D BFT variants. TSV based power and delay models were extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture. We propose a new OP3DBFT (Optimal Power and Performance 3DBFT) architecture with round-robin deflection routing (RROD) as power and performance optimal 2-layer 3D NoC architecture. OP3DBFT has symmetric link lengths and 75% of TSVs count reduced compared to the regular 2-layer 3D BFT topology. Results of our experiments show that the performance improved up to 1.39\(\times \) and 1.3\(\times \) in OP3DBFT with fewer TSV counts compared to the regular 2-layer 3D BFT for uniform and transpose traffic respectively. The OP3DBFT NoC architecture EDP (Energy delay product) was lower by 40% for uniform traffic and 48% for transpose traffic.

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

Several low-leakage repeater circuits for network-on-chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed staggered-Vt (SVT) repeater is compared with the novel dual-Vt domino (DTD) repeaters and sleep repeaters (SR). These circuits are compared with standard low-Vt (LVT) repeaters in a 32-bit link. Up to 70% and 61% power reduction was obtained in SVT and DTD repeaters, respectively. DTD repeaters are the most area-efficient ones, showing 40% reduction in total area of repeaters. Sleep repeaters are most area-consuming and less effective in high and moderate utilization rates, but comparable to SVT in terms of power for utilization rates below 2%, showing 72% power reduction.

Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the trade-off in concentration implementation and performance has not been well understood. In this paper, we describe cost-efficient implementations of concentration and show how external concentration provides a significant reduction in complexity (47% and 36% reduction in area and energy, respectively) compared to previous assumed integrated (high-radix) concentration while degrading overall performance by only 10%. Hybrid implementations of concentration is also presented which provide additional tradeoff between complexity and performance. To further reduce the cost of NoC, we describe how channel slicing can be used together with concentration. We propose virtual concentration which further reduces the complexity - saving area and energy by 69% and 32% compared to baseline mesh and 88% and 35% over baseline concentrated mesh.

Application-Specific Network-on-Chip synthesis with flexible router Placement

Power spectral analysis of fetal heart rate variability has been proposed to provide a non-invasive estimate of autonomic balance. However, there are few systematic data before birth. We therefore examined developmental changes in the frequency power spectrum at very low (0-0.04 Hz), low (0.04-0.15 Hz) and high frequencies (0.15-0.4 Hz), as well as the ratio of low- to high-frequency power (LF/HF), in chronically catheterized, healthy fetal sheep at 0.6 (n = 8), 0.7 (n = 7) and 0.8 gestational age (ga; n = 11). In a second study, 0.8 ga fetuses received either atropine (4.8 mg bolus, then 4.8 mg h(-1) for 30 min, n = 6) or 6-hydroxydopamine (20 mg ml(-1) at 2.5 ml h(-1) for 3 h; n = 9). Data were analysed by sleep state, defined by low-voltage-high-frequency (LV) or high-voltage-low-frequency (HV) EEG. Total spectral power increased with gestational age (P < 0.05), while LF/HF decreased from 0.6 to 0.7 ga. At 0.8 ga, heart rate and LF/HF were significantly higher during HV than LV sleep (P < 0.05). Consistent with this, although total spectral power was not significantly greater during HV sleep, there was a significant interaction between sleep state and frequency band (P = 0.02). Both atropine (P = 0.05) and 6-hydroxydopamine (P < 0.05) were associated with an overall reduction in spectral power but no significant effect on the LF/HF ratio. This study does not support substantial, consistent differences between the frequencies of sympathetic and parasympathetic activity in late-gestation fetal sheep.

Emissions and power characteristics of diesel engines on methyl soyate and diesel fuel blends

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This application- specific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design.

This paper proposes novel low-power full-adder cell to be used as Shannon adder in the neural network applications. By using the Shannon’s theorem, the gate count is reduced, thereby the total chip area gets minimized. Hence, the power also gets reduced to a considerable amount. The designs are implemented using synthesis tool which results in significant reduction in area and power for the modified Shannon-based full-adder cell when compared with multiplexing control input technique (MCIT)-based full-adder cell.

Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.

Referenceable mobile crowdsensing architecture: A healthcare use case

Network-on-Chip (NoC) architectures have been proposed as a promising alternative to classic bus-based communication architectures. In NoC design, power efficiency is a crucial concern that runs through the whole synthesis process, such as topology generation, mapping, routing, et al. However, it is hard to converge at the final layout generation stage since different stages have different design objects. In this paper, we present an incremental power-aware layout optimization method based on a Mixed Integer Linear Programming (MILP) model at post-layout stage in NoC design. Experimental results show that our optimization flow can achieve 23.3% power reduction on wires with a reasonable runtime while both the area and chip performance would not compromise.

In this paper one way of reducing the power consumption and the area of a finite impulse response (FIR) filter is presented. Using a standard toggle-based power estimation method combined with gate-level simulations and circuit synthesis we showed that we can achieve a significant area and power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for an actual submicron technology (130 nm) but this method can be utilized successfully for other technologies.

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <2% degradation in throughput. The implementation overhead of TVA is negligible.

Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.