IBM’s V Compiler

MIMOLA (Machine Independent Microprogramming Language) refers to both a design language and a design method. MSS1 was Zimmermann’s original software system; MSS2 is the current version at the University of Kiel. Honeywell also has a new version. The MIMOLA system includes scheduling, data path synthesis, and controller design. See also IIT Delhi’s Synthesis System— Marwedel is also involved with that system — and Honeywell’s V-Synth System, which adds a VHDL front end to MSS1.

Tsing Hua University’s synthesis system includes scheduling (ALPS) and data path synthesis (LYRA and ARYL).

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling, and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. Recent work has established the importance of behavioral synthesis in low power VLSI design. However, most of the algorithms that have been proposed separate these tasks and perform them sequentially, and are hence not able to explore the tradeoffs possible due to their interaction. We present an efficient algorithm for performing scheduling, clock selection, module selection, and resource allocation and assignment simultaneously with an aim of reducing the power consumption in the synthesized data path. The algorithm, which is based on an iterative improvement strategy, is capable of escaping local minima in its search for a low power solution. The algorithm considers diverse module libraries and complex scheduling constructs such as multicycling, chaining, and structural pipelining. We describe supply voltage and clock pruning strategies that significantly improve the efficiency of our algorithm by cutting down on the computational effort involved in exploring candidate supply voltages and clock periods that are unlikely to lead to the best solution. Experimental results are reported to demonstrate the effectiveness of the algorithm. Our techniques can be combined with other known methods of behavioral power optimization like data path replication and transformations, to result in a complete data path synthesis system for low power applications.

On-line testable data path synthesis for minimizing testing time

The University of California at Irvine’s VHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis.

OASIS is a cell-based silicon compiler system that supports rapid implementation of digital Application specific ICs (ASICs). The system automates the design process by taking a high-level language description and producing a layout of a testable IC. OASIS facilitates design of large digital systems on silicon and gives the designer sufficient control to enable exploration of the speed-versus-area design tradeoffs. The front end of OASIS is the LOGIC-III compiler that translates a high-level language description into a hierarchical netlist of gates. The LOGIC-III language is a PASCAL-like language that allows the designer to specify his design completely and in a uniform, consistent manner. The language supports both the logic synthesis for FSMs and combinational logic, and the structural/algorithmic synthesis of data paths and regular structures such as adders or multipliers. The OASIS system comprises an integrated set of tools for complete design, simulation, verification, layout and testing of ASICs. Experience with the system shows a marked increase in design productivity when compared with more traditional design techniques. The authors describe the system with its unique features and present some of the results of using OASIS in designing semi-custom ASICs. >

This was the first of two Carnegie Mellon University Design Automation (CMU-DA) systems. This CMU-DA system included scheduling, data path synthesis, controller design, module binding, and linking between the algorithmic level input description and the Register Transfer level design. See also Carnegie-Mellon’s (Second) CMU-DA System and Carnegie-Mellon’s System Architect’s Workbench — — both are successors to this system.

This was the second of two Carnegie Mellon University pesign Automation (CMU-DA) systems. This CMU-DA system included scheduling, data path synthesis, controller design, module binding, and linking between the algorithmic level and Register Transfer level behavioral representations. See also Carnegie-Mellon’s (First) CMU-DA System and CarnegieMellon’s System Architect’s Workbench — the predecessor and successor to this system. See also AT&T’s Algorithms to Silicon Project — McFarland and Kowalski were later involved with that project.

The recent progress of high level synthesis has illuminated an effective aid for system designers. To keep pace with the development of such an environment, there is a need to consider design for testability (DFT) during the synthesis process. This paper proposes a DFT scheme that can be coordinated with data path synthesis by an interactive trade-off process. The basis of this work is a system level testability model. To quantify the qualitative description of testability, a con- trollability measure and an observability measure is devel- oped. Based on these two measures, a procedure of trading- off between testing time and test hardware overhead is demonstrated. Featuring the ability to work on partial designs, this testing cost evaluation scheme is well suited to the demands of high level synthesis. Currently, simu- lation tools for obtaining testability measures have been completed and experiments have been conducted to vali- date this model.

The University of California at Berkeley’s HYPER system is aimed at synthesizing real-time applications, and includes transformations, scheduling, data path synthesis, module binding, and controller design.

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections. Consequently, we try to minimize the cost of interconnections first and then to group the variables to form memory modules later. For a number of benchmark problems, it has been shown that this approach is quite effective.

In this paper, we study the memory allocation problem in data path synthesis. We propose a register organization called circular FIFO as an alternative to register file organization. In comparison with register file organization, FIFO organization eliminates the overhead of address generation and decoding hardware. The memory allocation problem, based on the circular FIFO organization, has been solved efficiently using constraint logic and interval constraint programming.

A new algorithm named the time-zone algorithm for solving register allocation problem in the automatic data path synthesis is presented in this paper. The time-zone algorithm was developed from the left-edge algorithm with which the number of registers can be minimized. The time-zone algorithm was developed to minimize the number of registers as well as the interconnections and the number of multiplexers required for the registers. The experimental results obtained from testing several published examples show that the interconnections are improved and the number of multiplexers is reduced while at the same time the number of registers is still minimized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Complexity of fragmentable object bin packing and an application