On-line testable data path synthesis for minimizing testing time

As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from Data Flow Graph (DFG) and it is used for interconnect and congestion planning. A two step heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.

We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling, and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. Recent work has established the importance of behavioral synthesis in low power VLSI design. However, most of the algorithms that have been proposed separate these tasks and perform them sequentially, and are hence not able to explore the tradeoffs possible due to their interaction. We present an efficient algorithm for performing scheduling, clock selection, module selection, and resource allocation and assignment simultaneously with an aim of reducing the power consumption in the synthesized data path. The algorithm, which is based on an iterative improvement strategy, is capable of escaping local minima in its search for a low power solution. The algorithm considers diverse module libraries and complex scheduling constructs such as multicycling, chaining, and structural pipelining. We describe supply voltage and clock pruning strategies that significantly improve the efficiency of our algorithm by cutting down on the computational effort involved in exploring candidate supply voltages and clock periods that are unlikely to lead to the best solution. Experimental results are reported to demonstrate the effectiveness of the algorithm. Our techniques can be combined with other known methods of behavioral power optimization like data path replication and transformations, to result in a complete data path synthesis system for low power applications.

At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new approach to the allocation of multiport memories which minimizes hardware costs in ASIC datapath synthesis. The proposed approach, AMD, considers not only the access requirements of registers but also the lifetime of registers. The objective is to minimize the requirement of registers and multiport memory modules under a given resource constraints simultaneously. The minimization problem has been modeled as a 0-1 integer linear programming problem. This approach is illustrated with an example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process and generates a distributed test controller that aims to minimize area and power. The system has been implemented and favorable results are reported.

The recent progress of high level synthesis has illuminated an effective aid for system designers. To keep pace with the development of such an environment, there is a need to consider design for testability (DFT) during the synthesis process. This paper proposes a DFT scheme that can be coordinated with data path synthesis by an interactive trade-off process. The basis of this work is a system level testability model. To quantify the qualitative description of testability, a con- trollability measure and an observability measure is devel- oped. Based on these two measures, a procedure of trading- off between testing time and test hardware overhead is demonstrated. Featuring the ability to work on partial designs, this testing cost evaluation scheme is well suited to the demands of high level synthesis. Currently, simu- lation tools for obtaining testability measures have been completed and experiments have been conducted to vali- date this model.

One of the important steps that a semiconductor chip goes through is electrical testing, which typically is performed on an automated test equipment (ATE) platform. The primary goal of this step is to achieve maximum test coverage while minimizing testing time as much as optimal. There are various test methods used in testing, ranging from a simple continuity test to implementations such as built-in self-tests (BISTs) in which the chip is instructed to run internally and the test program checks for the result only when it is done. BISTs are, in a way, non-deterministic in nature; testing time can vary depending on the internal clock frequency at which the test is run and other factors based on the chip's operation. One way to optimize testing time of non-deterministic tests at ATE is to read the results register immediately on completion of the BIST execution, and not wait for a hard-coded amount of time to elapse - typically, an amount of time based on the slowest possible test execution to complete. This paper discusses a method that eliminates unnecessary time lost waiting for data that may have long arrived.

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents temperature aware low power scheduling under resource and latency constraints. We assume resources with different energy delay values are available. These resources are optimized in terms of energy for a certain delay, using variable supply voltage, multiple threshold voltages and sizing techniques. The proposed algorithms are based on temperature and power efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy scheduling when there is no temperature critical points. If a functional unit reaches a critical temperature, algorithm tries not to schedule any nodes in the data flow graph to high temperature resources, thus decrease the chip temperature. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 2 times the critical path delay and one of the resource temperature is critical the average power reduction is 50.8% and utilization of the hot resource is average 1%.

Much current research has focused on employing network-on-chips (NoC's) for communication among numerous cores on large scale SoC's. One side benefit of such designs is the potential to utilize this communication infrastructure with little modification for manufacturing test delivery. In this paper the authors present a test scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower rate test execution at the target cores. To achieve this, test data are interleaved over the network in a time division multiplexed (TDM) approach. Experimental results with the ITC'02 SoC benchmarks are proposed that show substantial test time reduction beyond single speed techniques. Further enhancements are presented that overcome some deficiencies in the simplest approach

Due to high dimensionality of face images and finite number of training samples, the linear subspace technique for face recognition pose challenges for better performance. In this paper, we compare the performance of linear subspace methods which involve the computation of scatter matrices for face recognition under illumination variation. The performance of these methods is evaluated in terms of classification accuracy, computational training and testing time. Extensive empirical experiments are performed to compare the performance using AR, Pie, Yale and YaleB face databases. In absence of sufficient number of training samples, classification accuracy of linear subspace methods deteriorate. Experimental results show that the performance of Dual LDA is best in terms of average classification accuracy. It is also observed that Fisherface takes minimum training time and both ERE and SVM takes minimum testing time. No linear subspace method outperforms others in terms of all performance measures.

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper, we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

Network teaching is to use computer equipment and Internet technology in the virtual space, through a certain method to implement the teaching method on the network, the perfection of the network teaching system can directly replace the traditional teaching method in the whole process of teaching. In order to solve the problem of system development, this paper carries out the demand analysis. First, the use of data flow graph technology, depicting information flow and data from the input to the output of the process of transformation; and then, the use of data dictionary technology, defining the relevant elements of the data flow diagram; finally, the use of tree structure diagram is represented by the administrator subsystem, teacher subsystem and student subsystem structure of the system. The requirement analysis system design the bridge of analysis and software, has laid a foundation for the system development.

An approach of a functional-level testability evaluation, based on controllability and observability measures (c.o.m.), is proposed. Using Rutman's system model, ordinary applied at the gate level, c.o.m are extended to the data-path level, to permit incorporation of testability constraints in the high-level synthesis stage. The approach of computing these c.o.m. is based on the reduced ordered binary decision diagram (ROBDD) circuit representation. It is shown how to identify untestable parts of a data path and how to evaluate its test cost. The insertion of a two-variable multiplexor, as a structural modification in the data path, is suggested to improve the c.o.m., and so, the test cost. To evaluate the impact of this transformation on the data-path testability, an objective function is proposed, appropriate for high-level synthesis. >

Along with the functional units, storage and interconnects also contribute significantly to the data path cost. This paper addresses the issue of reducing the storage and interconnect cost by allocating queues for storing variables. In contrast to the earlier works, we support regular cdfgs and multi-cycle functional units for queue synthesis. Initial results on HLS benchmark examples have been encouraging and show the potential of data path cost reduction using queue synthesis. A novel feature of our work is the formulation of the problem for a variety of FIFO structures with their own queueing criteria.