Estimating test cost during data path and controller synthesis with low power overhead

On-line testable data path synthesis for minimizing testing time

We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling, and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. Recent work has established the importance of behavioral synthesis in low power VLSI design. However, most of the algorithms that have been proposed separate these tasks and perform them sequentially, and are hence not able to explore the tradeoffs possible due to their interaction. We present an efficient algorithm for performing scheduling, clock selection, module selection, and resource allocation and assignment simultaneously with an aim of reducing the power consumption in the synthesized data path. The algorithm, which is based on an iterative improvement strategy, is capable of escaping local minima in its search for a low power solution. The algorithm considers diverse module libraries and complex scheduling constructs such as multicycling, chaining, and structural pipelining. We describe supply voltage and clock pruning strategies that significantly improve the efficiency of our algorithm by cutting down on the computational effort involved in exploring candidate supply voltages and clock periods that are unlikely to lead to the best solution. Experimental results are reported to demonstrate the effectiveness of the algorithm. Our techniques can be combined with other known methods of behavioral power optimization like data path replication and transformations, to result in a complete data path synthesis system for low power applications.

This paper presents non-scan design-for-testability techniques applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new DFT measure, and utilize the RT-level structure of the data path together with adding constants, for cost-effective re-design of the circuit to make it easily testable, without having to either scan any FF, or break loops directly. The non-scan DFT technique was applied to several data paths. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed, with marginal area overheads.

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymptotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored.

Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to allow plenty of options how to eventually realize a system. This allows for design exploration which in turn heavily relies on knowing the costs of different design configurations (with respect to hardware usage as well as firmware metrics). To this end, methods for cost estimation are frequently applied in industrial practice. However, currently used methods for cost estimation oversimplify the problem and ignore important features - leading to estimates which are far off from the real values. In this work, we address this problem for memory systems. To this end, we borrow and re-adapt solutions based on Machine Learning (ML) which have been found suitable for problems from the domain of Computer Vision (CV) - in particular age determination of persons depicted in images. We show that, for an ML approach, age determination from the CV domain is actually very similar to cost estimation of a memory system.

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Current cost estimation techniques have a number of drawbacks. For example, developing algorithmic models requires extensive past project data. Also, off-the-shelf models have been found to be difficult to calibrate but inaccurate without calibration. Informal approaches based on experienced estimators depend on estimators' availability and are not easily repeatable, as well as not being much more accurate than algorithmic techniques. We present a method for cost estimation that combines aspects of algorithmic and experiential approaches (referred to as COBRA, COst estimation, Benchmarking, and Risk Assessment). We find through a case study that cost estimates using COBRA show an average ARE of 0.09. Although we do not have the room to describe the benchmarking and risk assessment parts, the reader will find detailed information in (Briand et al., 1997).

Cost estimating entails gathering and evaluating historical data, as well as using quantitative models, methodologies, tools, and databases to forecast the cost of a program in the future. At the early stages of the building design process, the cost is considered one of the most important elements in making decisions. During the design phase of a project, cost estimating is quite essential. To compelet a construction project successfully, it is critical to design a usable model and method for cost estimation in construction projects. For the above reason, this study has developed a hybrid method to conduct an accurate cost estimation in construction projects in Iraq. This study also conducted a rigorous survey to find five main influential factors with thirty-six sub-factors in the Iraqi market. It was evaluated through previous studies, questionnaires, and surveys of twenty projects to build a matrix factors database for construction projects. This work gathered the construction cost factors from relevant research and expert views. In the second step, the researcher ranked the factors within the Importance Regression Ensemble Method then the K-Nearest Neighbor Method was applied to specify the effect of the near-effective factors on the cost. The outcome of this study will be helpful to construction professionals in estimating a construction project effectively.

An approach of a functional-level testability evaluation, based on controllability and observability measures (c.o.m.), is proposed. Using Rutman's system model, ordinary applied at the gate level, c.o.m are extended to the data-path level, to permit incorporation of testability constraints in the high-level synthesis stage. The approach of computing these c.o.m. is based on the reduced ordered binary decision diagram (ROBDD) circuit representation. It is shown how to identify untestable parts of a data path and how to evaluate its test cost. The insertion of a two-variable multiplexor, as a structural modification in the data path, is suggested to improve the c.o.m., and so, the test cost. To evaluate the impact of this transformation on the data-path testability, an objective function is proposed, appropriate for high-level synthesis. >

Rapid evaluation processes are required especially for government funded eco-friendly projects, which aim to create eco-friendly transport facilities for cyclists and pedestrians. These projects should be constructed massively and timely to increase the use of bicycle and pedestrian facilities. Because the global warming issues are increasingly threatening, the infrastructures should be developed to be more environment-friendly, in order to cope with natural disasters occurred due to these global warming issues. Therefore, evaluation methods should consider the effectiveness of both walking and biking benefits, including the complement of limitations caused by local differences such as traffic culture and environment. This study investigated and analysed studies and business cases related to cost estimations of environment-friendly transportation means in Korea and foreign countries. It decided on the items of cost estimation methods and suggested an estimation methodology for each item. As a result of this study, coded and standardized estimation methods for feasibility studies of pedestrian and bicycle-related transportation facilities are suggested and these lead to use and shorten the cost estimation processes in the feasibility studies for eco-friendly transport facilities.

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

OASIS is a cell-based silicon compiler system that supports rapid implementation of digital Application specific ICs (ASICs). The system automates the design process by taking a high-level language description and producing a layout of a testable IC. OASIS facilitates design of large digital systems on silicon and gives the designer sufficient control to enable exploration of the speed-versus-area design tradeoffs. The front end of OASIS is the LOGIC-III compiler that translates a high-level language description into a hierarchical netlist of gates. The LOGIC-III language is a PASCAL-like language that allows the designer to specify his design completely and in a uniform, consistent manner. The language supports both the logic synthesis for FSMs and combinational logic, and the structural/algorithmic synthesis of data paths and regular structures such as adders or multipliers. The OASIS system comprises an integrated set of tools for complete design, simulation, verification, layout and testing of ASICs. Experience with the system shows a marked increase in design productivity when compared with more traditional design techniques. The authors describe the system with its unique features and present some of the results of using OASIS in designing semi-custom ASICs. >

This paper addresses a testability evaluation approach applied to VLSI circuits at the data path level. The proposed approach uses new functional testability measures, which are based on the techniques of Reduced Ordered Binary Decision Diagrams (ROBDDs) representing functional primitives. These measures are: the Variable Testability Measure (VTM), for predicting the test-vector number of a data path and the controllability and observability measures, for identifying untestable parts in a data path. An objective function is developed, which enables estimation of area, delay and testability constraints of a data path. In this context, a structural modification in the data-path architecture is proposed, to make the design testable and/or to optimize the global cost determined by the objective function. >

Describes an approach to the synthesis of VLSI systems from their high-level behavioral descriptions into structural implementations. This approach integrates operation scheduling, data-path allocation, and control allocation of a traditional synthesis process. Therefore, the advantages from compacting the data path, for example, can be compared immediately with the possible expansion of the control logic to justify the compaction. The horizontal algorithm is designed to make decisions on what should be done in each synthesis step. When making such design decisions, it makes tradeoffs between the data path and control, resource sharing, and operation scheduling, as well as cost and performance. The experimental results show that under the same conditions, a horizontal approach performs better than a vertical approach with respect to overall system performance and estimated layout area. The proposed horizontal optimization algorithm was designed and implemented in computer-aided design and manufacturing. >