Implementation alternatives for dual rate control systems with command shaping

High-quality off-line rendering requires many features not natively supported by current commodity graphics hardware: wide smooth filters, high sampling rates, order-independent transparency, spectral opacity, motion blur, depth of field. We present a GPU-based hidden-surface algorithm that implements all these features. The algorithm is Reyes-like but uses regular sampling and multiple passes. Transparency is implemented by depth peeling, made more efficient by opacity thresholding and a new method called z batches. We discuss performance and some design trade-offs. At high spatial sampling rates, our implementation is substantially faster than a CPU-only renderer for typical scenes.

Peak-shape analysis of excited states in KCl Auger spectra

The present study evaluated the intelligibility of tape-recorded speech sentences and digitized speech sentences digitized at low (4 kHz), moderate (8 kHz), and high (16 kHz) sampling rates by young adults under different listening conditions (quiet versus noise). Twenty-four young adults participated as subjects. The tape-recorded speech sentences and digitized speech sentences were presented to each subject in quiet and in the presence of background speech babble at a signal-to-noise ratio of 0 dB. The subjects were instructed to immediately write down each sentence soon after they heard it. A 4×2 analysis of variance with repeated measures was performed to assess the effects of mode of speech and listening conditions on total number of words correctly transcribed. Results showed that the main effects for mode of speech and listening condition were statistically significant. The interaction effects of mode of speech by listening condition were also statistically significant. Pairwise comparisons showed that significantly more words were transcribed in the quiet condition than in the corresponding noise condition for all the modes of speech except for the digitized speech at high sampling rate (16 kHz). The implications of the results are discussed.

A new dual control scheme is proposed to the stroke and phase compensation on the displacement of linear compressor of a split-Stirling cryocooler. This dual controller has two connected stroke and phase control loops, whose dynamic models are identified experimentally. These loops individually provide corrections on the stroke and phase of the compressor displacement to follow a sinusoidal command. The experimental results show that the dual stroke and phase control system is robust to parameter changes and external disturbances.

Dual motor synchronization control is widely used. In this paper, the principle of variable frequency speed regulation of three-phase asynchronous motor is analyzed. And the control algorithm based on integral separation is established. By analyzing the vector control algorithm and acceleration curve, to establish the variable frequency control strategy. In order to analyze the motion curve of double motor and the ideal dynamic and static performance of the system, the construction of dual motor synchronization control system with Power Flex 525 frequency converter and AB Micro850 PLC is needed, and thus we can achieve the goal of high efficiency and good performance of dual motor synchronization control system.

In this paper, a mathematical modeling is set up based on the trigger equipment of light electric vehicle speed control system, and the unit step response curve of dual closed-loop speed control system is given by using the simulation software simulink. A conclusion can be drew that the unit step response quality index of dual closed-loop speed control system is generally good, but the maximum overshoot of this system is relatively large. Considering overall stability, this system should be adjusted. On the basis of these, a double closed-loop speed control system design plan is proposed with rotating speed differential negative feedback, and a rotating speed of negative feedback link is introduced in this system. The simulation results show that the maximum overshoot of this system is reduced by 32.37%, and the overall data shows that this system has excellent stability performance, and also the response speed of this system is guaranteed. Keywords-DC motor; simulink; speed regulating system; negative feedback

The use of consumer-electronics mobile terminals to decode and view digital video is constantly growing. Consumers expect from them a good quality of experience (QoE) during the complete viewing of the video content, which is not always possible due to the battery-operated nature of this type of devices. In this paper, a dual closed-loop control system is proposed to act on the CPU frequency such that, by default, it controls a QoE-related variable to be at its lowest valid level in order to save as much energy as possible. This energy savings are computed as an energy bonus (EB) that can be further used in moments of higher power consumption. Anyway, when the EB decreases below a dynamic threshold, the system switches to an exception mode in which it controls the EB to be enough to guarantee the expected playback lifetime at the expense of lowering QoE. Besides, the system can be configured by users to be more or less aggressive in risking lifetime vs QoE by adjusting the mode-switching threshold. Upon implementation in the operating system of a commercial development board, results show how the system is able to meet the desired lifetime with a reduction of up to 70% of the time with QoE restrictions with respect to a previous lifetime-guaranteeing approach. Furthermore, the worst-case computation-time overhead of the system is only a 4.2%.

In the recent few years, it is observed that in wireless communication there has been a rapid growth in terms of different communication standards/ technologies being used. Thus, to support different communication standards, flexible system should be used to convert the digital signal from one sample rate to another (up sampling or down sampling). The solution is the use of Software defined Radio (SDR), which is a reconfigurable radio communication system. Therefore the most critical and demanding element in the digital signal processing chain of an SDR is the Sample Rate Converter. At high sampling rate, the signals cannot be processed by using baseband signal processing unit. Instead of any unique air-interface, SDR simultaneously handles multiple air-interfaces of different wireless standards that require sample rates for baseband processing. Thus, in SDR, Sampling Rate Conversion (SRC) is an important functionality to provide synchronization between the ADC and baseband signal processor. This paper provides a review on various types of SRC circuits, where their design characteristics are analyzed and compared. The review is based on designing of Sample Rate converters on Field-Programmable Gate Array (FPGA) and Applications Specific Integrated Circuit (ASIC) platform. For FPGA based design, LUT, slices, FFT, and other hardware resource parameters are estimated to evaluate their performance. For ASIC, area, power and delay are considered for performance evaluation.

In this paper, it is shown that lower transmission/sampling rates can be used in human activity recognition using channel state information (F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> -scores > 85%) and that extremely high sampling rates are unnecessary once the system has been deployed. This is done by analysing the effects of interpolating different sampling rates on Wi-Fi dynamic channel state information for human activity recognition. While current research focuses on training and testing with homogeneous and very high sampling rates (> 100 Hz), this paper outlines some issues with higher sampling rates and explores the impact of training and testing with heterogeneous sampling rates in order to advance more towards joint communication and sensing, where one cannot be certain of the received data rate over time while not knowing the exact training set due to weight sharing in Federated Learning. This paper shows the effect of training and testing with heterogeneous sampling rates (including interpolated datasets) on convolutional neural networks in WiFi sensing.

In this paper, we report on the results of digital signal processing of LaBr3(Ce) detectors. The photomultiplier (PMT) output signals from two cylindrical LaBr3(Ce) detectors (1.5′′ diameter and 2′′ tall) were directly digitized with an ultrafast digitizer (sampling rate up to 4 GSample/s and 10-bits resolution) and the energy and timing information were extracted through offline analysis of the pulses. It is shown that at high sampling rates (4 GS/s) a simple integration of pulses is sufficient to reproduce the analogue energy resolution of the detectors (3.5% at 662 keV energy) and by employing a digital version of constant-fraction discrimination (CFD) timing a time resolution of 240 ps (FWHM) is achieved at the energy lines of 60Co. The effects of pulse sampling rate were studied, indicating a degradation of the performance of the detectors with reducing the pulse sampling rate. In particular, it was found that at sampling rates below 1 GS/s, the digital timing can be limited by the aliasing error. By using an anti-aliasing filter, a time resolution of 375 ps (FWHM) and an energy resolution of 3.5% at 662 keV were achieved with a sampling rate of 500 MS/s.

Successive approximation analog to digital converters (SARs) are widely used in electronic circuits because of good performance from the power consumption, resolution and speed points of view. Leakage currents and DAC incomplete settling limits the performance of these ADCs in low and high sampling rates respectively. This limits the range of the sampling rate in which a SAR ADC can be used and so the usage of this ADC in multi-purpose SoCs. In this paper a background calibration technique is used in order to improve the range of the SAR ADC sampling rate. It is shown that by utilizing this technique, the sampling rate can be improved in a range of from 50 kHz to 1 MHz for a 10-bit SAR ADC with ENOB > 9 bit which is designed and simulated in 90 nm CMOS technology with a 1.2 V supply voltage.

Currently, the use of speech recognition is increaseingly in many applications such as mobile device interaction, interactive voice response system, voice search, voice dictation and voice identification. The heart of such applications is speech features needed to represent input signals. However, in real applications, speech signals are sampled with various sampling rates. The different sampling rates of input speech lead to the different features. This makes the speech recognition rate dropping. Therefore, this paper proposes an independent resolution descriptor based on fractal codes obtained by fractal encoding and decoding processes. The encoding process extracts fractal codes from partitioned speech signals, whereas the decoding process reconstructs independent resolution speech signals from the fractal codes. This method can effectively reconstruct speech signals at any sampling rates, especially at a higher sampling rate, which is a grand challenge. The proposed method is evaluated the performance by testing with AN4 corpus of CMU Sphinx speech recognition engine. The experimental results show that the proposed method can improve the accuracy of speech recognition, even if the sampling rate of testing speeches differs from that of training speeches.

Research on sampling rate selection of sensors in offshore platform shm based on vibration

MRI currently is the most powerful medical diagnostic tomography system. It provides high resolution with high detail medical image. Its magnetization sensing is also free from radiation impact hence safe for the patient. However, the data acquisition process takes quite a long time with high-rate sampling. The sensing patient should stay still in the MRI sensing device for 20 to 40 minutes. It can affect claustrophobia for some patients. The high-rate sampling will also linearly affect the cost, which is considerably high. Hence, the research on enabling under-sampling MRI imaging has been raised. The main objective of under-sampling MRI Imaging is reducing the scanning time by under-sampling the data acquisition while at the same time the resulting qualified reconstructed image can be maintained. Compressive Sensing (CS) framework is one of the approaches that can be utilized on solving projection with less measurement. It can recover signals which have sparsity property. The signal is sparse if the signal being sensed has low information rate. Thus, the framework of Compressive Sensing matches under-sampling MRI Imaging. The sparsity requirement is closely related to the design of sensing matrix and dictionary on the Compressive Sensing framework. This paper presents analysis of two proposed sensing matrix designs for Under-sampling MRI Imaging: square sensing matrix and sorting-based sensing matrix designs. The proposed sensing matrix design is intended to appropriately sample the data measurement on certain sampling rate in frequency domain to maintain the quality of the reconstructed MRI image closely to the ground truth (full sampling MRI Imaging). The simulations show that both proposed sensing matrix designs are able to conduct under-sampling MRI Imaging for at least at 40% sampling rate with average of PSNR 27.72 and 33.07 respectively subject to the ground truth.

Time delay estimation is of great significance in multipath propagation to recover overlapped signals and identify the channel characteristics. However, achieving a high accuracy in this purpose may pose many problems in ultra-wideband (UWB) applications. In UWB systems, capturing a signal with high sampling rates cannot readily be done; hence classical methods for time delay estimation substantially lose their precision. To overcome this challenge, the authors incorporate a robust estimation approach and supplementary sampling process in a unified algorithm to retrieve time delays from signals with low sampling rates. Toward that pursuit, a model based least squares estimator is proposed as the main approach to calculate time delays and a modified method based on multiple signal classification (MUSIC) is also presented for comparison aim. Then, the authors have developed the algorithm by embedding two additional pre-processing steps of under sampling and interpolation to achieve a higher sampling rate and a better resolution. To show the high accuracy of work, root mean square error is computed in different values of time delay. Simulation and experiment results show the considerably higher precision of the proposed algorithm in comparison with presented MUSIC type method and also previously proposed methods in literature.