Implementation Issues in Turbo Decoding for 3GPP FDD Receiver

We describe UbiNetics implementation of turbo decoders for 3/sup rd/ generation mobile communications. A turbo encoder has been agreed as the channel coding technique for high rate traffic channels by the 3(/sup r/d) Generation Partnership Project (3GPP); a group of international manufacturers and operators working towards a world-wide standard for 3G mobile communications. At UbiNetics we decode these channels on fixed point DSPs. Presently a single 200 MHz Texas Instruments DSP from the C62x family can decode, with 4 iterations, traffic channels at rates beyond 200 kbits/s. This is achieved using processor non-specific software written in C. With optimisation of critical sub-functions in assembly language we estimate that it should be possible to decode channels at around 400 kbits/s on a single 200 MHz processor. We describe the issues involved in the fixed-point implementation of a turbo decoder. We discuss the design choices that need to be made regarding the form of the decoder, and justify with floating point simulation results the choices we made. We then describe issues involved in implementing a turbo decoder on a fixed-point processor with a limited amount of memory, and give details of the solutions we used. Comparisons of results from our workstation based floating point simulations and those achieved on the fixed-point target platform are presented. The performance of the two is shown to be virtually identical.

This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K < 4096.

Since the dynamic range of state metrics is limited due to the finitude of their quantization, it is needed to take an anti-overflow operation in the implementation of Turbo decoder. In traditional methods, plenty of calculations should be done for the anti-overflow protection in a single cycle, which greatly restricts the actual running clock frequency, thus to bring a strong impact on the final decoding throughput. In this paper, a novel anti-overflow method is proposed, to compare with the conventional methods, the proposed method can significantly increase the running clock frequency and achieve higher decoding throughput without losing any decoding performance.

ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based implementation of a high throughput flexible turbo decoder. It introduces turbo decoding application and proposes an Application-Specific Instruction-set Processor with SIMD architecture, a specialized and extensible instruction-set, and 6-stages pipeline control. The proposed ASIP is developed in LISA language and generated automatically using the Processor Designer framework from CoWare. The paper illustrates how the automatic generated RTL code of the ASIP can be adapted for a rapid prototyping on FPGA reconfigurable logic and memory resources. For a Xilinx Virtex-II Pro FPGA, a single ASIP prototype occupies 68% of FPGA resources and achieves a 6.3 Mbit/s throughput when decoding a double binary turbo code with 5 iterations.

This paper presents the implementation of a 3GPP standards compliant configurable turbo decoder on a GPU. The challenge in implementing a turbo decoder on a GPU is in suitably parallelizing the Log-MAP decoding algorithm and doing an architecture aware mapping of it on to the GPU. The approximations in parallelizing the Log-MAP algorithm come at the cost of reduced BER performance. To mitigate this reduction, different guarding mechanisms of varying computational complexity have been presented. The limited shared memory and registers available on GPUs are carefully allocated to obtain a high real-time decoding rate without requiring several independent data streams in parallel.

High hardware design and mask production costs dictate the need to reuse an architectural platform for as many applications as possible. Embedded multimedia portable devices are required to perform in real time a huge variety of different algorithms, ranging from audio and image processing, to channel coding, to video games and java virtual machines. Dynamically reconfigurable architectures are an effective means to cope with both requirements. However, their effective and efficient use today is hindered by a lack of methodology and tools to extensively explore the hardware/software (HW/SW) design space, without requiring software developers to have a deep knowledge of the underlying architecture. This paper describes one such methodology, which extends the software programming model to the design flow for a reconfigurable processor. Its effectiveness is shown with the case study of a turbo decoder for universal mobile telecommunications systems, in which a remarkable 11X speed-up and 4X reduction of energy requirements with respect to a pure software implementation has been obtained, by mapping the more computation-intensive kernels to the reconfigurable hardware.

Massive MIMO has been proposed as a means of achieving huge spectral efficiency in cellular networks. However, its implementation is usually based on linear precoding schemes using Channel State Information (CSI). For this reason, the use of the Time Division Duplex (TDD) mode is typically assumed since it removes the dependence on the number of antennas at the transmitter to acquire CSI. Unfortunately, most of the cellular network operate in the Frequency Division Duplex (FDD) mode in which the acquisition of CSI depends proportionally to the number of transmit antennas. For this reason, the implementation of Massive MIMO is handicapped to few transmit antennas for the current cellular networks. In this paper we study the use of reconfigurable antennas that can switch among a set of preset modes, i.e., radiation patterns, through Blind Interference Alignment schemes. We show that it is a solution to exploit a very large number of antennas at the transmit side, overcoming the bottleneck that today constitutes the acquisition of CSI in Massive MIMO systems operating in FDD mode.

The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO decoder is based on trace back algorithm (TBA) and saves area and power by replacing the FIFO memory with an additional transition metric unit (TMU). The paper presents the implementation of SOVA decoder for constraint lengths K=3, 4, and 5, describing the design methodology and evaluation environment. Simulation results are provided showing up to 20% power saving and 46% area saving compared to a conventional SOVA decoder implementation.

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE’s frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD’s balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18- $\mu \text{m}$ SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6–3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes.

Turbo codes are widely used in satellite and mobile communication systems for their strong error-correcting performance. However, conventional iterative decoders such as Log-MAP suffer from high complexity and exhibit error floors in short block-length regimes. To address this, a Reliability-Based Compact Direct Decoder (RCODD) algorithm has been proposed as a non-iterative alternative that leverages encoder state information and demodulator reliability metrics for efficient decoding. This paper presents the first hardware implementation of the RCODD algorithm on an FPGA, featuring a serial architecture optimized for minimal memory usage and logic complexity. Synthesized on a Zynq-7010 FPGA, the design achieves a BER of 0.7×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−4</sup> at 2 dB SNR for a 16,000-bit stream while consuming only 49% of available BRAM and 56% of LUTs. A 4-way parallel version of the architecture is also proposed and simulated, demonstrating a 3.8× reduction in latency while preserving decoding performance. Additionally, a fixed-point quantization study confirms that a 16-bit representation of reliability values introduces negligible error, offering further scope for area and power optimization. Comparative analysis with existing turbo decoder designs shows that the proposed RCODD-based architecture is uniquely positioned to serve low-power, high-reliability applications such as satellite telecommand systems, while remaining scalable to higher-throughput needs.

From the need of high performance, new wireless telecommunications standards such as WIMAX and LTE are using Turbo Codes as a forward error correction (FEC) choice. This work presents all steps for the implementation of a LTE standard turbo decoder, from algorithm to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm.

In the universal mobile telephony system (UMTS) the frequency division duplex (FDD) and time division duplex (TDD) modes have adjacent carriers at 1920 MHz. This creates adjacent channel interference (ACI) between the two different air interfaces. Since different duplexing modes are used, the implications for each system are different, with respect to capacity and coverage: these implications are investigated in the paper. The separation distance of the TDD and FDD base station and the load in each system are varied and a symmetrical speech service in both systems is considered, with non-ideal power control assumed. It is found that for an FDD cell radius of 1000 m, a TDD cell radius of 50 m and 10% maximal tolerable outage, the effects of ACI on capacity can be compensated by dynamically increasing the required power at each BS, without affecting the coverage.

In wireless communications, massive multiple-input multiple-output (MIMO) systems in which the base station (BS) is equipped with a large number of antennas can provide significant spectral and energy efficiency by means of simple signal processing. Therefore, massive MIMO is an attractive technology for next generation wireless communication systems and for green communications. There are two operation modes: time-division duplex (TDD) and frequency-division duplex (FDD) for massive MIMO systems, and the debate on the two modes is still discussed in the literature. The originator of massive MIMO systems, Marzetta, has presented the basic frame structures for both the TDD and the FDD modes. However, the basic frame structures do not carefully take the hardware impairments such as phase noise (PN) into account. In this paper, by taking the PN as the key hardware impairment into account, we recommend new and efficient frame structures for both the TDD and the FDD modes. The corresponding performance comparison between the two modes is also provided by using the data transmission efficiency (DTE) as the performance measurement. The comparison may help determine which mode should be used for massive MIMO systems.

Unlike the time-division duplexing (TDD) systems, the downlink (DL) and uplink (UL) channels are not reciprocal anymore in the case of frequency-division duplexing (FDD). However, some long-term parameters, e.g. the time delays and angles of arrival (AoAs) of the channel paths, still enjoy reciprocity. In this paper, by efficiently exploiting the aforementioned limited reciprocity, we address the DL channel state information (CSI) feedback in a practical wideband massive multiple-input multiple-output (MIMO) system operating in the FDD mode. In particular, the base station (BS) can transmit the FFT-based pilots with the carefully-selected phase shifts to align the DL paths. Then the user can rely on the so-called time-domain aggregate channel (TAC) to derive the estimate of the DL CSI. Next, with the knowledge about the second-order statistics of the DL channels, the user is also able to compute feedback of reduced dimensionality. We demonstrate that each user can just feed back one scalar number per DL channel path for the BS to recover the DL CSIs. Comprehensive numerical results corroborate our designs.

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.