Implementation of 2-Bit Channel Quantization for the STT-MRAM with Low-Reading-Margin MTJ

Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology which exhibits nonvolatility, high density, high endurance, and nano-second read and write times. These characteristics make STT-MRAM suitable for last-level cache and other embedded applications. The STT-MRAM bit-cell consists of a magnetic tunnel junction (MTJ) which is composed of two ferromagnetic layers (free and fixed layers) and one insulating layer in between. As STT-MRAM arrays become denser to meet cost and requirements of high performance computing, the distance between adjacent MTJ bits reduces. This aggravates the magnetic coupling from free and fixed layer of one MTJ bit to its neighbors. Even though magnetic coupling is expected to become stronger as MTJ scales down, its impacts on static and dynamic properties on MTJ is relatively unexplored. In this paper, we present a model of the magnetic field coupling in high-density MTJ arrays for three different types of MTJ stacks and evaluate the effect of magnetic field induced coupling on static and dynamic properties. Lastly, we show how process induced variations in MTJ characteristics affect the magnitude of magnetic coupling and their effect on the electrical characteristics of the STT-RAM arrays.

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing.

Spin-Torque-Transfer Magnetic Random Access Memory (STT-RAM) has the potential to become a universal memory due to its superior properties compared with conventional memory technologies. However, numerous challenges still remain before this technology becomes practical. Efforts to improve the performance of magnetic tunnel junctions (MTJs), the building block of STT-RAM, were made both from the structural and material aspects, with the results and discussions presented in this dissertation. MTJ structures with AlOx tunnel barriers were deposited using the Bias Target Ion Beam Deposition (BTIBD) technique. A CoFe/FeMn/CoFe trilayer with exchange bias (EB) coupling was developed and the underlying physics was studied. By controlling the sputtering voltage, the ferromagnetic (FM) electrode/barrier interface profiles could be tuned to improve the tunneling efficiency as well as other important electrical and magnetic properties. During the MTJ fabrication process, formation of the tunnel barrier is the most critical step. An effective way of detecting the bottom electrode oxidation was developed by simple low temperature magnetic measurement. MTJs using CoFeB/MgO/CoFeB were successfully fabricated by BTIBD with tunneling magnetoresistance (TMR) around 70%. MTJ performance was optimized by tuning the annealing conditions and other junction stack parameters. Preliminary work on doublebarrier MTJs (DBMTJs) demonstrated the capability of BTIBD to make DBMTJs with the two pinned layers either parallel or antiparallel for different applications. From a material perspective, MnAl thin film with PMA and other unique properties was explored for its potential application as the FM electrode for MTJs. The successful growth of magnetic τ-MnAl with the L10 structure and a record high saturation magnetization value on MgO(001) substrate confirmed the candidacy of MnAl as a promising MTJ FM electrode. Further magnetic and structural analysis of τ-MnAl revealed certain correlations between the chemical ordering and saturation magnetization. Post-deposition heat treatment, rapid thermal annealing (RTA) in particular, was found to be a very effective way of tuning the properties of thin-film τ-MnAl.

Probabilistic nature of magnetic tunnel junctions (MTJs) poses a new type reliability challenges for spin-transfer-torque MRAM (STT-MRAM). Switching current and thermal barrier need to be co-optimized to control bit error rate margins of STT-MRAM. This requires deeper understanding about thermal disturbance and soft write errors of MTJ devices. In this tutorial, we review basic mechanisms that govern the bit error rates of STT-MRAM and discuss the effect of the probabilistic nature of MTJ devices on STT-MRAM reliability engineering.

Magnetic tunnel junctions (MTJ) with MgO/Fe based interfaces and out-of-plane spin direction form the basis of present-day spin-transfer-torque magnetic random-access memory (STT-MRAM) devices. They are a leading type of nonvolatile memory due to their very long endurance times and lack of reliability problems. Many semiconductor devices, such as the field effect transistor or nonvolatile memories, have undergone fundamental changes in materials design as dimensional scaling has progressed. Here, we consider how the future scaling of the MTJ dimensions might affect materials choices and compare the performance of different tunnel barriers, such as 2D materials like h-BN with the existing MgO tunnel barriers. We first summarize key features of MgO-based designs of STT-MRAM. We then describe general aspects of the deposition of 2D materials and h-BN on metals. We compare the band structures of MgO and h-BN with their band gaps corrected for the GGA band error. The different absorption sites of h-BN on Fe or Co are compared in terms of physisorbtive or chemisorbtive bonding sites and how this affects their spin-polarized bands and the transmission magneto-resistance (TMR). The transmission magneto-resistance is found to be highest for the physisorptive sites. We look at how these changes would affect the overall TMR and how scaling might progress.

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures.

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

The read reliability of spin-transfer torque magnetic random access memory (STT-MRAM) is greatly hindered by a low sensing margin as a result of a small tunneling magneto-resistance ratio (TMR). Although the new generation of perpendicular anisotropy spin-orbit torque (SOT)-MRAM offers faster access speed and longer lifetime than STT-MRAM, its read performance is not improved or even deteriorated because of the additional resistance of SOT channel in the read path. In this letter, we propose two novel cell structures of SOT-MRAM, which consist of one/two transistors, two diodes, and two magnetic tunnel junctions (1T2D2MTJ/2T2D2MTJ) on a shared U-shaped anti-ferromagnet layer, enabling a self-referencing scheme. Thanks to the bent current channel, the opposite direction of the SOT current below the free layers can one-step switch different data states in compatibility with the existing fabrication process of SOT-MRAM. Combined with the 28 nm tech node and Verilog-A MTJ compact model, the simulation results show that our proposed MRAM cell significantly improves sensing margin and bit error rate over the conventional 2T1M cell, which is expected to become a high read performance solution.

Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation Power Analysis (CPA) attack strategy against STT-MRAM based cryptographic designs using a new power model. In our proposed attack methodology, an adversary exploits the power consumption patterns during the write operation of an STT-MRAM based cryptographic implementation to successfully retrieve the secret key. In order to validate our proposed attack technique, we mounted a CPA attack on MICKEY-128 2.0 stream cipher design consisting of STT-MRAM cells with Magnetic Tunnel Junctions (MTJs) as storage elements. The results of the experiments show that the STT-MRAM based implementation of the cipher circuit is susceptible to standard differential power analysis attack strategy provided a suitable hypothetical power model (such as the one proposed in this paper) is selected. In addition, we also investigated the effectiveness of state-of-the-art side-channel attack countermeasures for MRAMs and found that our proposed scheme is able to break such protected implementations as well.

The single event upset hardened design of spin transfer torque magnetic random access memory read circuits at 40 nm technology

The switching current density in a bit of spin transfer torque magnetic random access memory (STT-MRAM) has to be <;1 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for realistic application. The STT-MRAM using CoFeB magnetic tunnel junctions (MTJs) with perpendicular anisotropy are possible to match this target. In this paper, the switching properties in this system are investigated by a micromagnetic model. To simulate the perpendicular and in-plane hysteresis loops correctly, inhomogeneity of the perpendicular interfacial anisotropy constant K is introduced to the free layer of the MTJ. The calculated resistance versus applied current density curves of the bits are highly asymmetric, which agrees with experiment. The critical switching currents have dispersion due to the inhomogeneity of K. In addition, the simulation confirms the nucleation-type reversal process, and the reversal time decreases with increasing applied current.

Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.

In recent years, spin-transfer torque magnetoresistive random access memory (STT-MRAM) has gained a lot of interest as a promising memory candidate for future embedded applications. STT-MRAM possesses desirable memory attributes such as excellent readability, writability, stability, non-volatility, and unlimited endurance. Moreover, ITRS reports that STT-MRAM can endure 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cycle operations before breakdown thus meeting 10 yrs life-time. As shown in Fig. 1, STT-MRAM bitcell consists of one access transistor and one magnetic tunnel junction (MTJ) (1T-1R). One of the primary reliability concerns in STT-MRAM is the dielectric breakdown of the tunnel junction MgO in the MTJ known as time-dependent dielectric breakdown (TDDB). The thickness of MgO is on the order of 1nm and the voltage across the MTJ during write operation is approximately 0.7V resulting in electric field of ~10MV/cm across it which can induce TDDB. Thus, such high stress conditions can lead to lower breakdown time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) which can go even lower with further MgO thickness scaling. In addition to the hard breakdown (HBD) in MTJ which results in very low MTJ impedance and inability to function as memory, experimental results show that soft breakdowns (SBD) also exists. SBDs cause minor degradation in the MTJ resistance and they have shorter average time to appear compared to HBDs. In this paper, we explore in detail the physical mechanism behind both HBD and SBD, and using percolation model we estimate the time dependent degradation in the MTJ performance parameters such as tunneling magneto-resistance (TMR), write current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ), write-time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WR</sub> ) and lifetime (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LIFE</sub> ).

Random Access Memories: Magnetic

Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power. However, Spin Transfer Torque Magnetic RAM (STT-MRAM) suffers from three reliability issues, namely, read disturbance, write failure, and retention failure, that present significant challenges to its use as a reliable on-chip memory. All of these three reliability challenges become even more threatening with any increase in STT-MRAM cell temperature. Write operations are regarded as the main source of heat generation and temperature increase in STT-MRAM on-chip memories. This article first presents experiments to show how the heat generated by consecutive writes affects the reliability of an STT-MRAM on-chip cache. Then, it proposes the WiSE framework, an approach to reduce the STT-MRAM-based cache memory temperature and improve its reliability. WiSE utilizes the Reinforcement Learning (Reinforcement Learning (RL)) technique to detect high-density write operation patterns in STT-MRAM cache. To manage the write operations across the STT-MRAM caches, WiSE introduces a new temperature-aware replacement policy. The simulation results show that while WiSE imposes only about 1% performance overhead, it improves retention failure rate, read disturbance rate and write failure rate by 64%, 57%, and 47%, respectively, compared to Least Recently Used (Least Recently Used (LRU)) replacement policy.