Implementation of a robust virtual metrology for plasma etching through effective variable selection and recursive update technology

Virtual metrology (VM) is the prediction of end-of-batch properties (i.e., metrology data) using process variables and other information available for the process and/or the product (i.e., machine data) without physically conducting property measurement. VM (sometimes augmented with existing metrology) has been utilized in semiconductor process monitoring and control. Besides the economic benefit of replacing or reducing metrology tools, due to the instant availability of high frequency machine data, a good VM can actually provide better process monitoring and control performance compared to the same monitoring and control schemes based on the physical metrology data which often obtained at lower frequencies and usually with delays. In this paper, we propose a statistics pattern analysis (SPA) based VM approach for predicting sheet resistance using optical emission spectroscopy (OES) data. The advantageous properties of the SPA based VM are discussed. And the performance of the SPA based VM is compared with several commonly used VM algorithms in terms of prediction accuracy.

Plasma etch is a complex semiconductor manufacturing process in which material is removed from the surface of a silicon wafer using a gas in plasma form. As the process etch rate cannot be measured easily during or after processing, virtual metrology is employed to predict the etch rate instantly using ancillary process variables. Virtual metrology is the prediction of metrology variables using other easily accessible variables and mathematical models. This paper investigates the use of Gaussian process regression as a virtual metrology modelling technique for plasma etch data.

Plasma etch is a key process in modern semiconductor manufacturing facilities as it offers process simplification and yet greater dimensional tolerances compared to wet chemical etch technology. The main challenge of operating plasma etchers is to maintain a consistent etch rate spatially and temporally for a given wafer and for successive wafers processed in the same etch tool. Etch rate measurements require expensive metrology steps and therefore in general only limited sampling is performed. Furthermore, the results of measurements are not accessible in real-time, limiting the options for run-to-run control. This paper investigates a Virtual Metrology (VM) enabled Dynamic Sampling (DS) methodology as an alternative paradigm for balancing the need to reduce costly metrology with the need to measure more frequently and in a timely fashion to enable wafer-to-wafer control. Using a Gaussian Process Regression (GPR) VM model for etch rate estimation of a plasma etch process, the proposed dynamic sampling methodology is demonstrated and evaluated for a number of different predictive dynamic sampling rules.

In semiconductor manufacturing, metrology operations are expensive and time-consuming, for this reason only a certain sample of wafers is measured. With the need of highly reliable processes, the semiconductor industry is interested in developing methodologies covering the gap of missing metrology information. Virtual Metrology (VM) turns out to be a promising method; it aims to predict wafer and/or site fine metrology results in real time and free of costs. Using virtual measurements as the input of a sampling decision system (SDS), an optimal strategy for measuring productive wafers can be suggested. Since sampling decisions strongly depend on the accuracy of the VM system, it is a key requirement to monitor the reliability of the obtained predictions. In this paper, we present approaches for dynamically assessing VM reliability using real metrology data. A Bayesian dynamical linear model (BDLM) handles increasing VM model uncertainty over time. Model parameters are updated whenever new real measurements become available. VM prediction quality is monitored applying a probability integral transform (PIT) and scoring rules for predictive probability distributions. Inferring equipment health factors (EHF), unreliable predictions can be detected before being delivered to the SDS. Based on the likelihood of the predicted measurements, VM trust factors are introduced. A Bayesian model for the prediction precision matrix allows updating the virtual measurements' uncertainty whenever real measurements are available. Taking account of the proposed methods, one is led to an improved accuracy of the SDS.

Monitoring of plasma etch processes for fault detection is one of the hallmark procedures in semiconductor manufacturing. Optical emission spectroscopy (OES) has been considered as a gold standard for modeling plasma etching processes for on-line diagnosis and monitoring. However, statistical quantitative methods for processing the OES data are still lacking. There is an urgent need for a statistical quantitative method to deal with high-dimensional OES data for improving the quality of etched wafers. Therefore, we propose a robust relevance vector machine (RRVM) for regression with statistical quantitative features for modeling etch rate and uniformity in plasma etch processes by using OES data. For effectively dealing with the OES data complexity, we identify seven statistical features for extraction from raw OES data by reducing the data dimensionality. The experimental results demonstrate that the proposed approach is more suitable for high-accuracy monitoring of plasma etch responses obtained from OES.

The endpoint detection (EPD) is the most important technique in plasma etching process. In plasma etching process, the Optical Emission Spectroscopy (OES) is usually used to analyze plasma reaction. And Plasma Impedance Monitoring (PIM) system is used to measure the voltage, current, power, and load impedance of the supplied RF power during plasma process. In this paper, Real-Time Decision Making Algorithm is proposed to improve the performance of EPD in SiOx single layer plasma etching. To enhance the accuracy of the endpoint detection, both OES data and PIM data are utilized and a real-time decision making algorithm is applied. The proposed method successfully detected endpoint of silicon oxide plasma etching.

Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab.

Virtual metrology (VM) involves estimating a product’s quality directly from production process data without physically measuring it. This enables the product quality of each unit of production to be monitored in real time, while preserving the process efficiency. Initially developed for the semiconductor industry, VM has recently been examined for use in other industrial fields. VM is enabled by components such as quality estimators and drift detectors. It enhances various industrial applications such as machine control and sampling decision systems. The literature lacks a comprehensive summary and a systematic review of the state of the art in VM. To fill this gap, this study followed a systematic methodology to conduct a complete and structured literature review of VM. This paper presents a detailed analysis of the 199 papers that we identified based on our search and selection criteria. Following our methodological framework, we assigned these papers to categories and highlighted shortcomings. Finally, we discussed VM’s use in various industrial fields, underlining its potential for every manufacturing industry. This study and the proposed framework are useful for both practitioners and academicians since they raise crucial theoretical and managerial questions as well as provide suggestions for further research on this critical topic.

In this paper, a Virtual Metrology (VM) model is proposed to predict etch rate which is one of the most important etching profile in etch process. Error Back Propagation (EBP) neural network is used to make the VM for etch rate prediction.

Commercial quadrupole mass spectrometer (QMS) residual gas analyzers became available in the late 1960s and have been popular in R&D laboratories, but have found limited use in semiconductor manufacturing. To sample at pressures above 10−5 Torr with ppm sensitivity or better (relative to the total process pressure), differential pumping is usually required. The newly available, small, high-pressure QMS sensors can operate as high as 10–20 mTorr without differential pumping, but provide somewhat lower mass resolution and partial pressure sensitivity than a standard QMS. Applications in semiconductor manufacturing include equipment monitoring, process monitoring, and effluent analysis. Equipment monitoring can include qualification after preventative maintenance, rate-of-rise tests, and leak identification and detection. Usually the burning question is, Why won’t the vacuum chamber pump down? Other uses that are not usually considered include the qualification of replaceable parts: sputter cathodes, electrodes, lamps, shields, etc. In process monitoring, the key question is, Is this process running normally? A manufacturing monitor can be useful simply by providing a comparison between a well-behaved high-yield process and a marginal or failing process. Examples are given for physical vapor deposition (sputtering) processes, chemical vapor deposition, and plasma etching. The effluent from chemical vapor deposition and plasma etch processes can be analyzed to measure the efficiency of process gas utilization or to monitor the efficacy of abatement methods used for the removal of global warming gases.

Advanced Process Control (APC) is an important research area in Semiconductor Manufacturing (SM) to improve process stability crucial for product quality. In low-volume-high-mixture fabrication plants (fabs), Knowledge Discovery in Databases is extremely challenging due to complex technology mixtures and reduced availability of data for comparable process steps. High Density Plasma Chemical Vapor Deposition (HDP CVD) appears to be a process area in SM predestinated for application of Data Mining (DM). Enhancing physical metrology by predictive models leads to smart future fabs. Actual research focuses on Virtual Metrology (VM) using high sophisticated Machine Learning (ML) methods to model unknown functional interrelations and to predict the thickness of dielectric layers deposited onto a metallization layer of the manufactured wafers. Decision Trees (DT), Neural Networks (NN) and Support Vector Regression (SVR) have been investigated to maximize the accuracy of the regression. For data of various logistical granularities promising results have been achieved by implementing these statistical models.

In semiconductor manufacturing, the state of the art for wafer quality control is based on product monitoring and feedback control loops; the related metrology operations, that usually involve scanning electron microscopes, are particularly cost-intensive and time-consuming. It is therefore not possible to evaluate every wafer: commonly, a small subset of a productive lot is measured at the metrology station and delegated to represent the whole lot. Virtual Metrology (VM) methodologies aim to obtain reliable estimates of metrology results without actually performing measurement operations; this goal is usually achieved by means of statistical models, linking process data and context information to target measurements. In this paper, we tackle two of the most important issues in VM: (i) regression in high dimensional spaces where few variables are meaningful, and (ii) data heterogeneity caused by inhomogeneous production and equipment logistics. We propose a hierarchical framework based on ℓ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -penalized machine learning techniques and solved by means of multitask learning strategies. The proposed methodology is validated on actual process and measurement data from the semiconductor manufacturing industry.

Multi-step virtual metrology for semiconductor manufacturing: A multilevel and regularization methods-based approach

In semiconductor manufacturing processes, virtual metrology (VM) has been investigated as a promising tool to predict important characteristics of products. Although partial least squares (PLS) is a well-known modeling technique that can cope with collinearity and therefore applied to construction of VM, its prediction performance deteriorates due to changes in process characteristics. In particular, maintenance of equipment strongly affects the process characteristics and the prediction performance. In this paper, VM was developed by using locally weighted PLS (LW-PLS), which is a type of just-in-time modeling technique, and it was used to predict the etching conversion differential of an actual dry etching process. The industrial application results have shown that the developed VM based on LW-PLS is superior to the conventional VM based on the sequential update model and artificial neural network model. In particular, it has been confirmed that the LW-PLS-based VM can keep its high prediction performance even after the maintenance, i.e., replacement of parts.

Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges.