The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing

In TSV fabrication process, TSV depth measurement of all wafers is essential to maintain high yield and wafer quality. However, there are limits such as high cost and (low throughput using an actual metrology, i.e. scanning electron microscope (SEM), and only few wafers in a lot are monitored in practice. In this research, we presented a virtual metrology (VM) system for TSV depth measurement after etching process. The proposed VM system is based on PLS regression (PLSR) and neural networks (NN) using OES data to predict TSV depth. Real operational data taken during TSVs etching process along with 80 and 25 μm diameter TSVs are used in order to verify the quality of the prediction accuracy of the proposed VM model.

Semiconductor fabrication involves several sequential processing steps with the result that critical production variables are often affected by a superposition of affects over multiple steps. In this paper a Virtual Metrology (VM) system for early stage measurement of such variables is presented; the VM system seeks to express the contribution to the output variability that is due to a defined observable part of the production line. The outputs of the processed system may be used for process monitoring and control purposes. A second contribution of this work is the introduction of Elastic Nets, a regularization and variable selection technique for the modelling of highly-correlated datasets, as a technique for the development of VM models. Elastic Nets and the proposed VM system are illustrated using real data from a multi-stage etch process used in the fabrication of disk drive read/write heads.

Kernel approaches for fault detection and classification in PARR-2

Virtual Metrology (VM) refers to a technology that is able to conjecture product quality using important parameter data of production equipment and proper prediction schemes. In an automatic VM system (AVMS), VM Manager is the core of system's operations and the communication bridge among subsystems because it is responsible for distributing commands to each subsystem and possessing access privilege to the central database. This paper aims to develop a new kernel and several functional mechanisms for VM Manager so that the AVMS with refined VM Manager can have superior overall execution efficiency than the original one. A paradigm AVMS with the refined VM Manager for the TFT-LCD industry is constructed and tested. Integrated testing results validate that the developed new kernel and functional mechanisms of VM Manager can indeed achieve the design objectives.

Tremendous amounts of equipment parameters and sensor values were generated during modern semiconductor wafer manufacturing. These process data were utilized for early diagnosis of anomalies to prevent subsequent yield loss. However, process data from different steps and machines were highly customized that it is of great difficulties for traditional fault detection and classification (FDC) analysis to find a universal model to identify process excursions. In this paper, we present a neural network method with deep convolutional variational autoencoder structures which used reconstruction error as abnormal scores. This method exhibited a more reliable detection precision than FDC method and traditional anomaly detection algorithms. Furthermore, the reconstruction error of different sensors could be used to identify the root cause of abnormal processes. It was found that similarly structured networks could be applied to different processing steps, which enable this method to be accepted as a standard method to process data.

In semiconductor manufacturing, metrology operations are expensive and time-consuming, for this reason only a certain sample of wafers is measured. With the need of highly reliable processes, the semiconductor industry is interested in developing methodologies covering the gap of missing metrology information. Virtual Metrology (VM) turns out to be a promising method; it aims to predict wafer and/or site fine metrology results in real time and free of costs. Using virtual measurements as the input of a sampling decision system (SDS), an optimal strategy for measuring productive wafers can be suggested. Since sampling decisions strongly depend on the accuracy of the VM system, it is a key requirement to monitor the reliability of the obtained predictions. In this paper, we present approaches for dynamically assessing VM reliability using real metrology data. A Bayesian dynamical linear model (BDLM) handles increasing VM model uncertainty over time. Model parameters are updated whenever new real measurements become available. VM prediction quality is monitored applying a probability integral transform (PIT) and scoring rules for predictive probability distributions. Inferring equipment health factors (EHF), unreliable predictions can be detected before being delivered to the SDS. Based on the likelihood of the predicted measurements, VM trust factors are introduced. A Bayesian model for the prediction precision matrix allows updating the virtual measurements' uncertainty whenever real measurements are available. Taking account of the proposed methods, one is led to an improved accuracy of the SDS.

Advanced packaging has a challenge on its hands in dealing with reliability issues caused during singulation. Specifically, in the case of Wafer Level Chip Scale packaging (WLCSP) where the sawn die edge is the package edge and is exposed. WLCSP manufactured on the newer nodes are based on Ultra-low K dielectric material. This material is inherently porous and mechanically fragile. During the singulation step, there is a likelihood of creating chipping and delamination. Rudolph have developed a comprehensive approach to detecting defects generated at the laser grooving and saw process steps. There are two recommended approaches. The first approach is an inspection approach that is focused on detecting the defects after it has occurred. The second, a more sophisticated approach is to attempt to pre-empt occurrence of defects. In the first approach-die seal ring inspection, algorithms have been developed around the die seal ring to ensure the die integrity. These algorithms not only include the capability to detect the defect but also measure the defect size, defect position and frequency of defects. All of this is done while minimizing false defects that are typically found due to street and reticle artifacts that are often falsely detected as chipping. This enables customers to perform advanced disposition to ensure the optimal balance between shipping good die and preventing the shipment of potential reliability fails. The second approach — Kerf metrology and Saw control comprises of Fault detection and classification (FDC) to record equipment data during the singulation processes and inspection equipment to detect surface defects such as chips, delamination and cracks. The combination of FDC to monitor equipment performance and the ability to correlate Metrology/Inspection performance data enables customers to not only detect defects but preemptively eliminate them. Poorly singulated dies can now be analyzed all the way back to the process equipment signals. Once these signals are identified they can be monitored to prevent or alert operators of possible excursions. These analytics will help customers define and ramp robust processes, justify consumable costs and ultimately lead to a better understanding of this difficult and challenging process. Finally, specific YMS capabilities exist to align and analyze the collected equipment and process data.

Test of covariance changes without a large sample and its application to fault detection and classification

Semiconductor manufacturing comprises hundreds of consecutive unit processes. A single misprocess could jeopardize the whole manufacturing process. In current manufacturing environments, data monitoring of equipment condition, wafer metrology, and inspection, etc., are used to probe any anomaly during the manufacturing process that could affect the final chip performance and quality. The purpose of investigation is fault detection and classification (FDC). Various methods, such as statistical or data mining methods with machine learning algorithms, have been employed for FDC. In this paper, we propose an artificial immune system (AIS), which is a biologically inspired computing algorithm, for FDC regarding semiconductor equipment. Process shifts caused by parts and modules aging over time are main processes of failure cause. We employ state variable identification (SVID) data, which contain current equipment operating condition, and optical emission spectroscopy (OES) data, which represent plasma process information obtained from faulty process scenario with intentional modification of the gas flow rate in a semiconductor fabrication process. We achieved a modeling prediction accuracy of modeling of 94.69% with selected SVID and OES and an accuracy of 93.68% with OES data alone. To conclude, the possibility of using an AIS in the field of semiconductor process decision making is proposed.

Virtual metrology (VM) involves estimating a product’s quality directly from production process data without physically measuring it. This enables the product quality of each unit of production to be monitored in real time, while preserving the process efficiency. Initially developed for the semiconductor industry, VM has recently been examined for use in other industrial fields. VM is enabled by components such as quality estimators and drift detectors. It enhances various industrial applications such as machine control and sampling decision systems. The literature lacks a comprehensive summary and a systematic review of the state of the art in VM. To fill this gap, this study followed a systematic methodology to conduct a complete and structured literature review of VM. This paper presents a detailed analysis of the 199 papers that we identified based on our search and selection criteria. Following our methodological framework, we assigned these papers to categories and highlighted shortcomings. Finally, we discussed VM’s use in various industrial fields, underlining its potential for every manufacturing industry. This study and the proposed framework are useful for both practitioners and academicians since they raise crucial theoretical and managerial questions as well as provide suggestions for further research on this critical topic.

This paper discusses several practical issues encountered when applying principal component analysis (PCA) to fault detection and classification (FDC). Those issues presented a challenge to the success of PCA-model based process monitoring. Weighted PCA is proposed to address the issues. Two forms of weighted PCA are discussed: sample-wise and variable-wise. Sample-wise weighted PCA is used to address issues with model updating. By adapting models with process changes, the long-term validity of a PCA model can be maintained. We also propose to deal with drift and shift features separately. Variable-wise weighted PCA is used to incorporate process and sensor knowledge. PCA models built this way require less maintenance and result in better FDC performance. We performed comparison studies on plasma etcher FDC. We have shown that weighted PCA can adapt to process drift, reduce the occurrence of false alarms and make the models easy to maintain.

In semiconductor manufacturing, the state of the art for wafer quality control is based on product monitoring and feedback control loops; the related metrology operations, that usually involve scanning electron microscopes, are particularly cost-intensive and time-consuming. It is therefore not possible to evaluate every wafer: commonly, a small subset of a productive lot is measured at the metrology station and delegated to represent the whole lot. Virtual Metrology (VM) methodologies aim to obtain reliable estimates of metrology results without actually performing measurement operations; this goal is usually achieved by means of statistical models, linking process data and context information to target measurements. In this paper, we tackle two of the most important issues in VM: (i) regression in high dimensional spaces where few variables are meaningful, and (ii) data heterogeneity caused by inhomogeneous production and equipment logistics. We propose a hierarchical framework based on ℓ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -penalized machine learning techniques and solved by means of multitask learning strategies. The proposed methodology is validated on actual process and measurement data from the semiconductor manufacturing industry.

Multi-step virtual metrology for semiconductor manufacturing: A multilevel and regularization methods-based approach

In the context of automated analysis of eye fundus images, it is an important common fallacy that prior works achieve very high scores in segmentation of lesions, and that fallacy is fueled by some reviews reporting very high scores, and perhaps some confusion with terms. A simple analysis of the detail of the few prior works that really do segmentation reveals scores between 7% and 70% in sensitivity for 1 FPI. That is clearly sub-par with medical doctors trained to detect signs of Diabetic Retinopathy, since they can distinguish well the contours of lesions in Eye Fundus Images (EFI). Still, a full segmentation of lesions could be an important step for both visualization and further automated analysis using rigorous quantification or areas and numbers of lesions to better diagnose. I discuss what prior work really does, using evidence-based analysis, and confront with segmentation networks, comparing on the terms used by prior work to show that the best performing segmentation network outperforms those prior works. I also compare architectures to understand how the network architecture influences the results. I conclude that, with the correct architecture and tuning, the semantic segmentation network improves up to 20 percentage points over prior work in the real task of segmentation of lesions. I also conclude that the network architecture and optimizations are important factors and that there are still important limitations in current work.

The proposed paper presents an equipment level FDC system for the optimization and anomaly detection of semiconductor equipment. Through the equipment level FDC(Fault Detection and Classification) system, various data in the equipment can be converted into meaningful and accurate analysis data through context mapping to facilitate analysis of the management and condition of the equipment. In addition, it is possible to proactively identify and respond to problems at the equipment level before identifying and responding to problems on the host by processing data of diverse equipment in real time.