Virtual metrology for TSV etch depth measurement using optical emission spectroscopy

Semiconductor fabrication involves several sequential processing steps with the result that critical production variables are often affected by a superposition of affects over multiple steps. In this paper a Virtual Metrology (VM) system for early stage measurement of such variables is presented; the VM system seeks to express the contribution to the output variability that is due to a defined observable part of the production line. The outputs of the processed system may be used for process monitoring and control purposes. A second contribution of this work is the introduction of Elastic Nets, a regularization and variable selection technique for the modelling of highly-correlated datasets, as a technique for the development of VM models. Elastic Nets and the proposed VM system are illustrated using real data from a multi-stage etch process used in the fabrication of disk drive read/write heads.

Virtual metrology of semiconductor PVD process based on combination of tree-based ensemble model

Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab.

In semiconductor manufacturing processes, virtual metrology (VM) has been investigated as a promising tool to predict important characteristics of products. Although partial least squares (PLS) is a well-known modeling technique that can cope with collinearity and therefore applied to construction of VM, its prediction performance deteriorates due to changes in process characteristics. In particular, maintenance of equipment strongly affects the process characteristics and the prediction performance. In this paper, VM was developed by using locally weighted PLS (LW-PLS), which is a type of just-in-time modeling technique, and it was used to predict the etching conversion differential of an actual dry etching process. The industrial application results have shown that the developed VM based on LW-PLS is superior to the conventional VM based on the sequential update model and artificial neural network model. In particular, it has been confirmed that the LW-PLS-based VM can keep its high prediction performance even after the maintenance, i.e., replacement of parts.

Virtual Metrology (VM) refers to a technology that is able to conjecture product quality using important parameter data of production equipment and proper prediction schemes. In an automatic VM system (AVMS), VM Manager is the core of system's operations and the communication bridge among subsystems because it is responsible for distributing commands to each subsystem and possessing access privilege to the central database. This paper aims to develop a new kernel and several functional mechanisms for VM Manager so that the AVMS with refined VM Manager can have superior overall execution efficiency than the original one. A paradigm AVMS with the refined VM Manager for the TFT-LCD industry is constructed and tested. Integrated testing results validate that the developed new kernel and functional mechanisms of VM Manager can indeed achieve the design objectives.

In semiconductor manufacturing, metrology operations are expensive and time-consuming, for this reason only a certain sample of wafers is measured. With the need of highly reliable processes, the semiconductor industry is interested in developing methodologies covering the gap of missing metrology information. Virtual Metrology (VM) turns out to be a promising method; it aims to predict wafer and/or site fine metrology results in real time and free of costs. Using virtual measurements as the input of a sampling decision system (SDS), an optimal strategy for measuring productive wafers can be suggested. Since sampling decisions strongly depend on the accuracy of the VM system, it is a key requirement to monitor the reliability of the obtained predictions. In this paper, we present approaches for dynamically assessing VM reliability using real metrology data. A Bayesian dynamical linear model (BDLM) handles increasing VM model uncertainty over time. Model parameters are updated whenever new real measurements become available. VM prediction quality is monitored applying a probability integral transform (PIT) and scoring rules for predictive probability distributions. Inferring equipment health factors (EHF), unreliable predictions can be detected before being delivered to the SDS. Based on the likelihood of the predicted measurements, VM trust factors are introduced. A Bayesian model for the prediction precision matrix allows updating the virtual measurements' uncertainty whenever real measurements are available. Taking account of the proposed methods, one is led to an improved accuracy of the SDS.

Samsung SDSThe purpose of virtual metrology (VM) in semiconductor manufacturing is to predict every wafer’s metrological values based on its process equipment data without an actual metrology. In this paper, we propose novelty detection-based reliability estimation models for VM in order to support flexible utilization of VM results. Because the proposed model can not only estimate the reliability of VM, but also identify suspicious process variables lowering the reliability, quality control actions can be taken selectively based on the reliance level and its causes. Based on the preliminary experimental results with actual semiconductor manufacturing process data, our models can successfully give a high reliance level to the wafers with small prediction errors and a low reliance level to the wafers with large prediction errors. In addition, our proposed model can give more detailed information by identifying the critical process variables and their relative impacts on the low reliability.

This paper proposes to develop a data-driven via's depth estimator of the deep reactive ion etching process based on statistical identification of key variables. Several feature extraction algorithms are presented to reduce the high-dimensional data and effectively undertake the subsequent virtual metrology (VM) model building process. With the available on-line VM model, the model-based controller is hence readily applicable to improve the quality of a via's depth. Real operational data taken from a industrial manufacturing process are used to verify the effectiveness of the proposed method. The results demonstrate that the proposed method can decrease the MSE from 2.2 × 10−2 to 9 × 10−4 and has great potential in improving the existing DRIE process.

Background: E-beam metrologies, both critical dimension scanning electron microscope metrology and defect scan metrology, have been playing a very critical role in gating patterning quality. SEM images can provide rich visual information for engineers to do qualitative and quantitative analyses. However, the low e-beam metrology tool throughput makes it impossible to obtain SEM images for larger area. Monte Carlo-based SEM image simulations or other SEM image simulations require postlithography or postetch pattern three-dimensional structures as prerequisite, and the simulation speed is not sufficiently fast for full chip implementation. Aim: We aim to develop machine learning SEM models with sufficient accuracy and speed for full chip application in semiconductor manufacturing environment. Approach: We have proposed a virtual SEM metrology solution based on U-Net neural network with physics-based feature maps as model input. With information in aerial image space encoded properly, SEM images of both postlithography and postetch can be predicted accurately enough for practical applications using our proposed virtual SEM metrology models. Equipped with GPUs, the machine learning-based SEM image models are fast enough to make it possible to realize full chip SEM generation from post-OPC data. Results: Our machine learning SEM image models can predict SEM images with normalized cross correlation around 0.95 in reference to ground truth SEM images, each SEM image (512 × 512 in size) takes about 800 ms using single CPU, and the speed can be accelerated to about 10 ms with single GPU. Conclusions: Using U-Net structure and physics-based feature maps as model inputs, machine learning-based SEM image models can be developed. The models are sufficiently accurate and fast to find their applications in semiconductor manufacturing, and they can be used as independent model for OPC data verification or generate SEM images as reference for SEM defect scan metrology.

Advanced Process Control (APC) is an important research area in Semiconductor Manufacturing (SM) to improve process stability crucial for product quality. In low-volume-high-mixture fabrication plants (fabs), Knowledge Discovery in Databases is extremely challenging due to complex technology mixtures and reduced availability of data for comparable process steps. High Density Plasma Chemical Vapor Deposition (HDP CVD) appears to be a process area in SM predestinated for application of Data Mining (DM). Enhancing physical metrology by predictive models leads to smart future fabs. Actual research focuses on Virtual Metrology (VM) using high sophisticated Machine Learning (ML) methods to model unknown functional interrelations and to predict the thickness of dielectric layers deposited onto a metallization layer of the manufactured wafers. Decision Trees (DT), Neural Networks (NN) and Support Vector Regression (SVR) have been investigated to maximize the accuracy of the regression. For data of various logistical granularities promising results have been achieved by implementing these statistical models.

In this paper, a Virtual Metrology (VM) model is proposed to predict etch rate which is one of the most important etching profile in etch process. Error Back Propagation (EBP) neural network is used to make the VM for etch rate prediction.

In semiconductor manufacturing, the state of the art for wafer quality control is based on product monitoring and feedback control loops; the related metrology operations, that usually involve scanning electron microscopes, are particularly cost-intensive and time-consuming. It is therefore not possible to evaluate every wafer: commonly, a small subset of a productive lot is measured at the metrology station and delegated to represent the whole lot. Virtual Metrology (VM) methodologies aim to obtain reliable estimates of metrology results without actually performing measurement operations; this goal is usually achieved by means of statistical models, linking process data and context information to target measurements. In this paper, we tackle two of the most important issues in VM: (i) regression in high dimensional spaces where few variables are meaningful, and (ii) data heterogeneity caused by inhomogeneous production and equipment logistics. We propose a hierarchical framework based on ℓ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -penalized machine learning techniques and solved by means of multitask learning strategies. The proposed methodology is validated on actual process and measurement data from the semiconductor manufacturing industry.

Multi-step virtual metrology for semiconductor manufacturing: A multilevel and regularization methods-based approach

Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges.

This paper discussed the virtual metrology (VM) modelling of multi-class quality to describe the relationship between the variables of a production machine's condition and the estimated/forecasted product quality soon after finishing the machine processing. Applications of PCA and LASSO technique of the Sparse modelling were introduced to define the multi-dimensional quality. Because the high accuracy and quick computations are required for the VM modelling, in this study, the PCA-LASSO combination was applied before building the VM models based on the kernel SVM (kSVM), particularly the linear kernel for real-time use. As the result of evaluation of a CVD (Chemical vapor deposition) process in an actual semiconductor factory, LASSO and linear-SVM could reduce the scale of the machine variable's set and calculation time by almost 57% and 95% without deterioration of accuracy even without PCA. In addition, as the PCA-LASSO, the multi-dimensional quality was rotated to the orthogonality space by PCA to summarize the extracted variables responding to the primary independent hyperspace. As the result of the PCA-LASSO combination, the scale of machine variables extracted was improved by 83%, besides the accuracy of the linear-SVM is 98%. It is also effective as the pre-process of Partial Least Square (PLS).