Statistical key variable analysis and model-based control for improvement performance in a deep reactive ion etching process

Recently, demands for nanochannels have been increasing in biological and nanofluidic applications. In this paper, a fabrication process that produces a nanochannel with a width of less than 20 nm and a high aspect ratio is proposed. For the versatility of channel pattern design, focused ion beam (FIB) direct writing is applied for mask fabrication. A metal mask pattern is fabricated using localized ion implantation method and is used for a deep reactive ion etching (DRIE) process. A process condition for minimum undercut in the DRIE process is determined. The proposed method is applied to the fabrication of nanochannels with various dimension and patterns.

Laser interference lithography (LIL) is a technique that allows maskless patterning of large areal periodic nano/micro structures. The LIL pattern is often used as an etch barrier to pattern SiO2 intermediate layer in the fabrication process of high aspect ratio silicon nano/micro structures by deep reactive ion etching process (DRIE) with SiO2 etch barrier. In this study, a method to fabricate high aspect ratio nanograting structures by direct DRIE process of silicon substrate using LIL pattern without intermediate layer was developed as a simple and cost-effective fabrication process. To fabricate high aspect ratio silicon nanograting with high pattern fidelity, a simulation method to predict the cross sectional profile of photoresist (PR) pattern after exposure and development processes was investigated, and the LIL processing conditions were selected to obtain optimized cross sectional profile of PR pattern without residual layer based on the simulation results. To minimize the side wall defects during the DRIE process due to the deterioration of LIL pattern etch barrier, the processing conditions of DRIE process including etching gas, etching gas ratio, passivation time and power were optimized. Finally, a silicon nanograting with a grating pitch of 780 nm and height of 2.42 µm (aspect ratio: 6) was fabricated via the developed direct DRIE process with LIL pattern.

Development of a novel cloud-based multi-tenant model creation service for automatic virtual metrology

In TSV fabrication process, TSV depth measurement of all wafers is essential to maintain high yield and wafer quality. However, there are limits such as high cost and (low throughput using an actual metrology, i.e. scanning electron microscope (SEM), and only few wafers in a lot are monitored in practice. In this research, we presented a virtual metrology (VM) system for TSV depth measurement after etching process. The proposed VM system is based on PLS regression (PLSR) and neural networks (NN) using OES data to predict TSV depth. Real operational data taken during TSVs etching process along with 80 and 25 μm diameter TSVs are used in order to verify the quality of the prediction accuracy of the proposed VM model.

Virtual metrology (VM) predicts on-wafer properties, such as thickness and uniformity, using equipment data (e.g., sensors, constants) and potentially on-wafer properties or predictions from previous steps. While much literature is devoted to developing VM models, maintaining them (e.g., so they can be used for months in production) presents a different set of challenges. Behavior of equipment can change over time, causing degradation of VM models. Maintenance events can abruptly reset sensors and process conditions, invalidating VM models. In addition, sensor noise, sensor imperfection and aging parts can disturb performance of VM models. While some of these issues can be addressed during modeling by incorporating certain variables that capture the dynamics associated with these issues, others are harder to foresee. Resolving these issues may require tuning the models as they age or manually rebuilding the models after they become ineffective. To mitigate these problems, techniques including monitoring residual error and tool degradation, compensating for sensor reset and residual error, and auto-retraining models can significantly help VM models maintain their performance during deployment.

Background: E-beam metrologies, both critical dimension scanning electron microscope metrology and defect scan metrology, have been playing a very critical role in gating patterning quality. SEM images can provide rich visual information for engineers to do qualitative and quantitative analyses. However, the low e-beam metrology tool throughput makes it impossible to obtain SEM images for larger area. Monte Carlo-based SEM image simulations or other SEM image simulations require postlithography or postetch pattern three-dimensional structures as prerequisite, and the simulation speed is not sufficiently fast for full chip implementation. Aim: We aim to develop machine learning SEM models with sufficient accuracy and speed for full chip application in semiconductor manufacturing environment. Approach: We have proposed a virtual SEM metrology solution based on U-Net neural network with physics-based feature maps as model input. With information in aerial image space encoded properly, SEM images of both postlithography and postetch can be predicted accurately enough for practical applications using our proposed virtual SEM metrology models. Equipped with GPUs, the machine learning-based SEM image models are fast enough to make it possible to realize full chip SEM generation from post-OPC data. Results: Our machine learning SEM image models can predict SEM images with normalized cross correlation around 0.95 in reference to ground truth SEM images, each SEM image (512 × 512 in size) takes about 800 ms using single CPU, and the speed can be accelerated to about 10 ms with single GPU. Conclusions: Using U-Net structure and physics-based feature maps as model inputs, machine learning-based SEM image models can be developed. The models are sufficiently accurate and fast to find their applications in semiconductor manufacturing, and they can be used as independent model for OPC data verification or generate SEM images as reference for SEM defect scan metrology.

In this study, a method for fabrication of high aspect ratio silicon nanopillars is presented.The method combines liquid flame spray production of silica nanoparticle agglomerateswith cryogenic deep reactive ion etching. First, the nanoparticle agglomerates, having adiameter of about 100 nm, are deposited on a silicon wafer. Then, during the subsequentcryogenic deep reactive ion etching process, the particle agglomerates act as etch masks andsilicon nanopillars are formed. Aspect ratios of up to 20:1 are demonstrated. Themasking process is rapid, cheap and has the potential to be scaled up for largeareas. Three other structured silicon surfaces were fabricated for comparison. Allfour surfaces were utilized as desorption/ionization on silicon (DIOS) sampleplates. The mass spectrometry results indicate that nanopillar surfaces maskedwith the liquid flame spray technique are well suited as DIOS sample plates.

Influence of deep reactive ion etching process parameters on etch selectivity and anisotropy in stacked silicon substrates for fabrication of comb-type MEMS capacitive accelerometer

It is reported for the first time a process technology to fabricate sub-100 nm silicon nano-channels with ultra high aspect ratio (~160) for micro fluidics, nano-filtration and pathogen detection applications. A novel double passivation deep reactive ion etching process has been developed to realize ultra high aspect ratio silicon nano-channels which is further narrowed by deposition of polysilicon and thermally oxidized to form sub-100 nm buried nano-channels. This technology further provides for in-situ capping of the nano channels which offers significant stress-relief at the top of the nano-channels during subsequent glass bonding and packaging process. By providing in-situ capping capability for the channels we also eliminate potential leakage issues due to poor bonding contact. This channel capping also helps in preventing breakage of the high aspect ratio structures under high anodic bonding pressure. Though the present work was targeted for biological applications, it can easily be used for mainstream MEMS and NEMS applications such a RF resonators, Sensors and Actuators.

Duringthe deep reactive ion etching process, the sidewalls ofa silicon mold feature rough wavy structures, which can be transferredonto a polydimethylsiloxane (PDMS) microchannel through the soft lithographytechnique. In this article, we utilized the wavy structures of PDMSmicrochannel sidewalls to initiate and cavitate bubbles in the presenceof acoustic waves. Through bubble cavitation, this acoustofluidicapproach demonstrates fast, effective mixing in microfluidics. Wecharacterized its performance by using viscous fluids such as poly(ethyleneglycol) (PEG). When two PEG solutions with a resultant viscosity 54.9times higher than that of water were used, the mixing efficiency wasfound to be 0.92, indicating excellent, homogeneous mixing. The acoustofluidicmicromixer presented here has the advantages of simple fabrication,easy integration, and capability to mix high-viscosity fluids (Reynoldsnumber: ∼0.01) in less than 100 ms.

Near term and future experiments in high-energy physics and molecular biology will require radiation hard and fast detectors with sensitive border to cope with the increasingly stringent research requirements. 3D detectors, with vertical electrodes penetrating through the entire silicon substrate have drawn high interests for these applications due to their unique advantages such as ultra-fast time response, edgeless capability and radiation hardness. In addition, the through-wafer electrode technology can provide the possibility to connect 3D detectors on a wafer level via 3D interconnects [1, 2]. Since its introduction by S. Parker and C. Kenney in 1995 [3], several laboratories have begun research on 3D processing technology. Besides their advantages, fabrication of 3D detectors remains non-trivial and has only been possible since the successful developments in wafer bonding and deep reactive ion etching (DRIE). The edgeless capability is achieved by etching a through-wafer trench that surrounds an entire detector, and is then filled with highly doped silicon to form an active edge electrode. The process wafer must be bonded to a support wafer prior to the etching. Moreover, following polysilicon deposition, the process wafer is subject to severe mechanical stress and risk of cracking, making the support wafer even more necessary. At SINTEF MiNaLab, the first prototype run started in 2007, with an emphasis to demonstrate the feasibility to fabricate full 3D detectors with active edge on a production scale. During this run, wafer bonding was used to facilitate the etching of trenches and to provide mechanical support to the process wafer. A deep reactive ion etching process was also developed to etch 14 μm round holes through 250 μm thick silicon wafer. The first run is now fully completed and preliminary results are promising. Good p-n junction characteristics have been shown, and a leakage current of less than 0.5 nA per pixel was measured on selected devices. SINTEF is now the second laboratory who has successfully fabricated 3D detectors with active edge and is the first who attempted to fabricate on a production scale. This paper discusses the processing issues encountered in this first prototype run, with a focus on two important processes; wafer bonding and deep reactive ion etching (DRIE).

A double-sided wet etch process has been proposed to fabricate vertical structures in 〈1 0 0〉 oriented silicon substrate. Both sides of a {1 0 0} silicon wafer have been patterned identically along the 〈1 1 0〉 direction, and etched using potassium hydroxide (KOH) solution. By precisly controlling the etch time, using etch-timer structure and additive control, structures with smooth and vertical {1 1 0} sidewalls have been fabricated at the edges of a rectangular opening without undercut. Rectangular through-holes, bridges and cantilevers have been constructed using the proposed process. The measured average surface roughness of the vertical sidewall was 481 nm, which has been further reduced to 217 nm and 218 nm by postetching using a KOH–IPA and TMAH–Triton mixture, respectively. Slanted {4 1 1} planes exposed at the concave corners during the vertical etch process have been successfully removed or diminished by the postetching process. A bridge structure with a high aspect ratio of 39:1 has been fabricated, and cantilevers without undercutting were successfully constructed by applying the compensation technique. The proposed process can potentially be utilized in place of the deep reactive ion etching process for the fabrication of structures having vertical through-holes, such as through-silicon vias, high aspect ratio springs and filters for microfluidic applications.

This paper reports on the development of out-of-plane electrostatic microactuators whose stiffness can be actively tuned through an integrated mechanism based on in-plane forces acting on bending flexures. The devices combine out-of-plane flexures and drives with in-plane flexures and electrodes. The out-of-plane electrodes are asymmetric interdigitated fingers obtained from a simple, stepped deep reactive ion etching process contrasting with other more complex gap-refilling approaches. The in-plane drives consist of conventional interdigitated combs.

We describe a laser-based technique to monitor the time multiplexed deep reactive ion etching of silicon. Mask and substrate etch rates, as well as mask quality information, can be extracted simultaneously and in-situ using a single laser beam system.

Sidewall roughness measurement is becoming increasingly important in the micro-electromechanical systems and nanoelectronics devices. Atomic force microscopy (AFM) is an emerging technique for sidewall scanning and roughness measurement due to its high resolution, three-dimensional imaging capability and high accuracy. We report an AFM sidewall imaging method with a quartz tuning fork (QTF) force sensor. A self sensing and actuating force sensor is fabricated by microassembling a commercial AFM cantilever (tip apex radius ≤10 nm) to a QTF. The attached lightweight cantilever allows high-sensitivity force detection (7.4% Q factor reduction) and sidewall imaging with high lateral resolution. Owing to its unique configuration, the tip of the sensor can detect sidewall surface orthogonally during imaging, which reduces lateral friction. In experiments, sidewalls of a micro-electro-mechanical system (MEMS) structure fabricated by deep reactive ion etching process and a standard step grating are scanned and the sidewall roughness, line edge roughness and sidewall angles are measured.