Implementation of FPGA based DPWM-Digital PI Closed Loop Controller for Voltage Regulation

The use of very high-resolution digital pulse width modulators (DPWMs) for high frequency dc-dc converters has been steadily increasing in recent years. However, the resolution of the DPWM formed by counters and comparators is limited when the switching frequency rise above MHz range. Given this limitation, new strategies for DPWM architectures are being designed to increase the resolution of the signals. This article proposes two new DPWMs architectures with the aim of increasing the resolution of trigger signals using field programmable gate arrays (FPGAs). The first proposed architecture is a hybrid DPWM, which integrates a clock manager and a delay line. For this architecture, the delay line is configured using FPGA intellectual properties (IP) blocks. This delay stage allows a fine resolution in the picosecond scale. In addition, an alternative solution has been implemented to generate two signals, the main signal and its complementary one, including high resolution for the dead time, which is also configurable. Both architectures have been tested through static and dynamic tests on two FPGAs of different costs, an Artix-7 (low-cost) and a Kintex-UltraScale 7 (high-cost) by Xilinx.

This paper proposes the design of a novel Modified Counter based Digital Pulse Width Modulation generator to analyze the performance of the closed-loop DC-DC buck converter. The closed-loop DC-DC buck Converter uses the Proportional Integral controller to regularize the output voltage and the bio-inspired algorithms namely Particle Swarm Optimization and Ant Colony Optimization are considered for the generation of the optimal values for the PI gains namely KP and KI. Conventionally, the switching of the buck converter is controlled by the PWM signals that exhibit complexity in design. The updated Digital Pulse Width Modulation techniques were suitable for voltage regulation at the cost of high clock frequency requirement, increase in the design area for real implementation, and the trade-off between the switching frequency and the component size of the buck converter. To overcome these, the modified Counter based Digital Pulse width modulation that generates the high switching frequency DPWM is developed in HDL. Then the proposed technique is validated in the closed-loop PI-based DC-DC buck converter using the System Generator MATLAB SIMULINK. To regularize the voltage output, the PI controller is included along with the optimization algorithms such as Particle Swarm Optimization and Ant Colony Optimization to optimize the PI gains. The time transient analysis of the proposed method exhibits improvement in the ACO based design compared to the PSO based method. The power and area are manipulated by using the Cadence and Xilinx tools

The duty cycle in digital pulse width modulation (DPWM) whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and interconnects are superimposed on the on-time. The duty-cycle-increment phenomenon affects the regulation performance of converters, especially when the delays are the same magnitude level as switching period. In this paper, a compensation method based on tool command language commands is used to offset the propagation delays. Furthermore, the DPWM applies a counter, phase locked loop, and carry chain to constitute segmented delay-line, while it maintains a wide duty cycle range and a high time resolution. This DPWM is implemented by a low-cost field-programmable gate array Cyclone IV. It achieves a good linearity where R2 is 0.9949 for an 11-bit, 9.375 MHz switching frequency DPWM. The duty cycle range is from 1.52% to 97.81%. Meanwhile, the time resolution and average duty difference are 53 ps and 3.08%, respectively.

PurposeThe model for digitally controlled three-phase pulse width modulation (PWM) boost rectifiers is a sampled data model, which is different from the continuous time domain models presented in previous studies. The controller, which is tuned according to the model in continuous time domain and discretized by approximation methods, may exhibit some unpredictable performances and even result in unstable systems under some extreme situations. Consequently, a small-signal discrete-time model of digitally controlled three-phase PWM boost rectifier is required. The purpose of this paper is to provide a simple but accurate small-signal discrete-time model of digital controlled three-phase PWM boost rectifier, which explains the effect of the sampling period, modulator and time delays on system dynamic and improves the control performance.Design/methodology/approachBased on the Laplace domain analysis and the waveforms of up-down-count modulator, the small signal model of digital pulse width modulation (DPWM) in the Laplace domain is presented. With a combination of state-space average and a discrete-time modeling technique, a simplified large signal discrete time model is developed. With rotation transformation and feed-forward decoupling, the large-signal model is decoupled into a single input single output system with rotation transformation. Then, an integrated small signal model in the Laplace domain is constructed that included the time delay and modulation effect. Implementing the modified z-transform, a small-signal discrete-time model is derived from the integrated small signal model.FindingsIn a digital control system, besides the circuit parameters, the location of pole of open-loop transfer function is also related to system sampling time, affecting the system stability, and the time delay determines the location of the zero of open-loop transfer function, affecting the system dynamic. In addition to the circuit parameters discussed in previous literature, the right half plane (RHP) zero is also determined by the sampling period and the time delay. Furthermore, the corner frequency of the RHP zero is mainly determined by the sampling period.Originality/valueThe model developed in this paper, accounting for the effect of the sampling period, modulator and time delays on the system dynamic, give a sufficient insight into the behavior of the digitally controlled three-phase PWM rectifier. It can also explain the effect of sampling period and control delay time on system dynamic, accurately predict the system stability boundary and determine the oscillation frequency of the current loop in critical stable. The experimental results verify that the model is a simple and accurate control-oriented small-signal discrete-time model for the digitally controlled three-phase PWM boost rectifier.

There is an interest in industry to miniaturize the power converters, and increasing the switching frequency yields to a reduced sized of the reactive components and thus to a smaller size of the circuit. However, this increased switching frequency has resulted in the need for digital pulse width modulators (DPWM) with high resolution to improve the performance of the control circuit. When the switching frequency increases, the requirement of a very high-performance DPWMs is necessary because DPWMs resolution is limited. This work presents and compares two architectures of hybrid DPWM where the finest resolution is achieved using standard logic components of vendor’s libraries. The main advantages of the proposal are that the implementation does not require any placement and routing effort and the resolution is very high (80 ps) even when implemented in a low- cost Xilinx Artix-7 FPGA.

In this paper, a digital pulse width modulator (DPWM) is analyzed from the point of view of susceptibility to radio-frequency interference (RFI). The chosen DPWM architecture is based on the hybrid delay-line/counter scheme commonly used in the digital control of switched-mode power supplies (SMPSs). This paper focuses on the DPWM performance degradation in the presence of electromagnetic interference (EMI), and for this purpose a DPWM with time resolution down to 350 ps has been designed and manufactured in a standard 0.35- mum complementary metal-oxide semiconductor technology. Measurements and analytical analyses are presented for both EMI effects on the internal generated clock signal and on the PWM duty-cycle precision. The immunity degradation mechanisms are investigated by means of an analytical approach, demonstrating that the PWM susceptibility is more strictly related to its functional design rather than to the implemented topology. The effects of clock and duty-cycle jitter induced by RFIs are finally verified using a simulation model on a digitally controlled buck converter, highlighting the importance of such issue on steady-state performances of SMPSs.

This paper presents a novel digital pulse width modulator (DPWM) structure with higher time resolution and lower input clock frequency, which is especially suitable for high frequency digitally controlled DC-DC switching converters. For the proposed DPWM, two multi-phase clock arrays are generated which have relatively close frequencies, and the time-inserting method is also utilized. The FPGA based simulation results show that, the proposed DPWM can achieve the time resolution of around 30ps and the equivalent 12-bits precision when the input dual-clock frequencies are 100MHz and 105MHz at 5MHz switching frequency.

A novel digital controller for boost power factor correction converter is proposed to achieve high power factor and fast dynamic response. A method of direct duty cycle calculation is adopted to improve the power factor. The prediction module is adopted to estimate the track of the output voltage and the inductor current of next switching cycle in advance to improve the dynamic response. A multiplex successive approximation analog-to-digital converter (ADC) is designed to aim high resolution via little hardware resource. Meanwhile, a novel digital pulse width modulator (DPWM) is realized to improve the regulation linearity. The boost PFC converter with proposed digital controller based on the field programmable gate array (FPGA) has been implemented. Experimental results indicate that the proposed digital controller can achieve high power factor more than 0.98, the dynamic response under load variation is about 80ms and the output voltage overshoot is about 6%.

This paper presents a digital controller architecture oriented to IC implementation. The classical digital pulse width modulator (D-PWM), using digital analog converter (DAC), is replaced with a Sigma-Delta (/spl Sigma//spl Delta/) modulator based on pulse frequency modulator (PFM) technique. Results of an investigation from a prototype for DC-DC converter, in terms of simulated and experimental performances, are reported, together with harmonic frequency investigation. The control function design is implemented on a field programmable gate array (FPGA). As a consequence of good agreement between simulated and experimental results, the proposed architecture realizes a digital control loop with dynamic performances comparable to analog control systems.

Hybrid DPWM implementation using coarse and fine programmable ADLL

This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization

In this paper, a pulse-modulated power-recycling polar transmitter with dual-phase aliasing-free digital pulsewidth modulation (DPWM) for 4G long term evolution (LTE) is presented. This implementation is capable of achieving high linearity and efficiency by using concurrent power recycling and dual-phase aliasing-free DPWM. A prototype transmitter system is constructed with commercially available components. Measurements using a 16-QAM 20-MHz bandwidth LTE signal at 836.5 MHz achieved 41.2% drain efficiency at 23.8 dBm output power level while passing adjacent channel leakage ratio requirements without using digital pre-distortion. Compared to conventional DPWM, the aliasing-free DPWM signal provides a more linear output.

We study end-to-end quantization in digitally controlled MHz-range GaN DC–DC converters, spanning the analog-to-digital converter (ADC), fixed-point controller, and digital pulse-width modulator (DPWM). A simulation framework sweeps ADC and DPWM resolutions across buck, boost, and inverting buck–boost converters at 1, 5, and 10 MHz, reporting regulation bias, output ripple, and limit-cycle occurrence. A simple metric ρ compares the DPWM step (mapped to V_out) to the ADC least-significant bit and accurately predicts the onset of limit cycles: designs with ρ≥1 avoid limit cycles in all surveyed cases. The results yield practical rules: boost and buck–boost require finer DPWM than buck due to larger ∂V/∂D; dithering and first-order sigma–delta (ΣΔ) modulation provide roughly one to two effective DPWM bits at 1 MHz; and increasing switching frequency tightens timing margins but can be offset by modest DPWM resolution or reduced digital delay. Validation includes analytic–simulated slope agreement, ρ–versus–limit-cycle slices, and robustness to parasitic spreads, ADC noise, and jitter. These findings provide concise, quantitative guidance for selecting ADC and DPWM resolutions to meet ≤10–20 mV ripple targets without limit cycles in MHz GaN converters.

This paper presents a PID controller design for voltage-mode DC-DC buck converter. Based on the mathematical derivations and verified by using behavioral models, the digital PID controller is induced to improve the phase margin of DC-DC buck converter. Based on the information of voltage error between feedback voltage and reference voltage, the behavior model for the DC-DC buck converter of voltage-mode with ADC, digital PID controller and digital pulse-width modulator (DPWM) is built to verify the system responses by using MATLAB Simulink.

Wide-bandgap semiconductor power devices are being adopted to increase efficiency and switching frequency for power converters. This requires a demand for higher resolution digital pulsewidth modulation (DPWM) in digitally controlled power converters. This is because, in a digitally controlled dc–dc converter, steady-state limit-cycle oscillations can exist if the resolution of DPWM is less than the ADC resolution. This article proposes a cost-competitive, high-performance, functionally integrated with a small package-sized, a complete direct digital synthesis-based DPWM architecture to achieve a high resolution, linear, monotonic behavior, and extremely fast frequency hopping ability. This article presents a detailed analysis of the new DPWM architecture. Simulation and experimental results are presented to verify the analysis. This article also discusses the various advantages and numerous applications addressed by the proposed method.