Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

In this paper, we present the performance analysis of the 32×32 crosspoint queued (CQ) switch. The CQ switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of credit based control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin and frame based round robin matching), are analyzed and compared. The results obtained for the CQ switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. Also, original iterative method for CQ switch throughput calculation under the uniform traffic is presented. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases, but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round robin based algorithms become a better choice for implementation due to their simplicity, small hardware requirements and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm. The proposed iterative method for throughput calculation gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.

Performance of a Generic Non-blocking Packet Switch

In orthopedic surgery department, multiple surgeries are carried out in the same operating room every day. Each surgery may have a random duration, differs from the scheduled time, which results in room idle time and patient waiting time. One of the major factors affecting the idle and waiting times is the schedule of surgeries in the operating room. To better sequence of surgeries to reduce idle time and waiting time, an effective performance evaluation method is needed. Although discrete event simulation can be used to evaluate the performance of surgery schedules, it suffers from long simulation time, which makes difficult in scheduling optimization. In this paper, an analytical model to evaluate the performance of operating room schedules in orthopedic surgery department is introduced. Using such a model, the expected idle time and waiting time for a given surgery schedule can be calculated accurately. Such a work provides substantial easiness for optimization of operating room schedules and investigation of the impact of different schedules.

In multistage parallel interference cancellation, the tentative decisions for different users at each stage are mutually correlated, and they are also correlated with Gaussian noise. By taking the correlations into consideration and employing Price's theorem, an analytical model is proposed to refine the variance evaluation of the final decision variable. It is shown that the refined variance is very close to that obtained by simulation and can improve the accuracy in bit error rate evaluation.

A model-based Digital Twin to support responsive manufacturing systems

The rapid growth of the Internet and the demand for carrying mixed mode traffic to deliver the commodity services, voice and data, at reasonable cost, to end users has put new pressures on the designers of switches and routers. The traditional architectures of routers with shared memory or crossbar are inefficient and fall short in their ability to meet this challenge. The need for faster optical switches fuelled by this rising demand is fraught with risks and fundamental physics problems that need to be addressed. We first examine the problem of designing a switch fabric that forms the core of the router as a multivariate optimization problem and in that context examine the limitations of the traditional crossbar or shared-memory approaches. We present a novel architecture that utilizes a combination of both space and time division multiplexing to deliver higher orders of throughput for a given switch size.

As data centers enter the exascale computing era, the traffic exchanged between internal network nodes, increases exponentially. Optical networking is an attractive solution to deliver the high capacity, low latency, and scalable interconnection needed. Among other switching methods, packet switching is particularly interesting as it can be widely deployed in the network to handle rapidly-changing traffic of arbitrary size. Nanosecond-reconfigurable photonic integrated switch fabrics, built as multi-stage architectures such as the Clos network, are key enablers to scalable packet switching. However, the accompanying control plane needs to also operate on packet timescales. Designing a central scheduler, to control an optical packet switch in nanoseconds, presents a challenge especially as the switch size increases. To this end, we present a highly-parallel, modular scheduler design for Clos switches along with a proposed routing scheme to enable nanosecond scalable scheduling. We synthesize our scheduler as an application-specific integrated circuit (ASIC) and demonstrate scaling to a 256 × 256 size with an ultra-low scheduling delay of only 6.0 ns. In a cycle-accurate rack-scale network emulation, for this switch size, we show a minimum end-to-end latency of 30.8 ns and maintain nanosecond average latency up to 80% of input traffic load. We achieve zero packet loss and short-tailed packet latency distributions for all traffic loads and switch sizes. Our work is compared to state-of-the-art optical switches, in terms of scheduling delay, packet latency, and switch throughput.

Performance analysis of packet switches with input and output buffers

Simulators and empirical profiling data are often used to understand how suitable a specific hardware architecture is for an application. However, simulators can be slow, and empirical profiling-based methods can only provide insights about the existing hardware on which the applications are executed. While the insights obtained in this way are valuable, such methods cannot be used to evaluate a large number of system designs efficiently. Analytical performance evaluation models are fast alternatives, particularly well-suited for system design-space exploration. However, to be truly application-specific, they need to be combined with a workload model that captures relevant application characteristics. In this paper we introduce PISA, a framework based on the LLVM infrastructure that is able to generate such a model for sequential and parallel applications by performing hardware-independent characterization. Characteristics such as instruction-level parallelism, memory access patterns and branch behavior are analyzed per thread or process during application execution. To illustrate the potential of the framework, we provide a detailed characterization of a representative benchmark for graph-based analytics, Graph 500. Finally, we analyze how the properties extracted with PISA across Graph 500 and SPEC CPU2006 applications compare to measurements performed on x86 and POWER8 processors.

Multi-objective Early-stage Design of Automotive Hybrid Assembly Lines

Performance evaluation of the augmented data vortex switch fabric: An all-optical packet switched interconnection network

The simulation model of the photonic switch designed for optical packet switching networks is presented in this paper for the first time. At first the scheme and the algorithm of operating the photonic switch are considered. Then the simulation model implemented as the program written in Python is proposed. This program reproduces the process of functioning of the considered photonic switch. The expressions for finding the time of packet transmission are presented in the work. They are used in the program and influence on output data such as buffer size and time to wait for a packet in the queue. The dependences of the optical buffer size on the throughput of the communication channel and load are presented in numerical results section. The results of 16×16 photonic switch simulation are considered in this section as the example. For this switch average value of maximum buffer size in dependence on input load and two different throughputs of communication channels 1Tbps and 100Gbps has been calculated. The optical packet length has been 1500 bytes.

This paper describes the architecture, functionality and performance of an experimental ATM switch being developed at the Telecom Australia Research Laboratories as part of its investigations into the broadband ISDN. The proposed switch architecture consists of parallel omega networks preceded by a Batcher bitonic sorting network. The switching fabric has no internal cell buffering. Cell buffering is provided only on the switch outputs for cells simultaneously contending for the same output port. The switch fabric and cell buffers include mechanisms for providing prioritized servicing of queued cells and prioritized discarding of cells based on priority fields contained within the cell header. Components of the switch are currently being implemented in 2 μm CMOS VLSI.

Packet contention is a major issue in asynchronous optical packet switching networks. Optical buffering, which is implemented by fiber delay lines (FDLs), is fundamental to many optical switch implementations for resolving contention. Most existing optical buffering implementations are output-based and require a huge amount of FDLs as well as larger switch sizes, which impose extra cost on the overall system. In this paper, we consider a shared optical buffering architecture which can reduce the buffer size at a switch. We propose an analytical model to evaluate the packet loss probability and the average delay For shared buffers at a single switch. We then compare the performance of output buffers to shared buffers under different granularities of FDLs. We observe that, by choosing an appropriate granularity, the shared buffering scheme can significantly reduce packet loss with much smaller switch sizes and fewer FDLs than the output buffering architecture. The accuracy of the analytical model is also confirmed by extensive simulation

— Packet contention is a major issue in asynchronous optical packet and burst switching networks. Optical buffering, which is implemented by fiber delay lines (FDLs), is fundamental to many optical switch implementations for resolving contention. Most existing optical buffering implementations are output-based and require a huge amount of FDLs as well as larger switch sizes, which impose extra cost on the overall system. In this paper, we consider shared optical buffering which can reduce the buffer size at a switch. Since no previous study is available to analyze the performance of asynchronous architectures with shared buffers, we propose an analytical model to evaluate the packet loss probability and the average delay for shared buffers at a single switch. We then compare the performance of output buffers to shared buffers under different granularities of FDLs. We observe that, by choosing an appropriate granularity, the shared buffering scheme can significantly reduce packet loss with much smaller switch sizes and fewer FDLs than the output buffering architecture. The accuracy of the analytical model is also confirmed by extensive simulation. I.