Improvement of high current density PCB design on a high end server system

For the same blocking voltage rating and on-state resistance, Silicon Carbide (SiC) MOSFETs die is thinner and smaller compared to Si counterpart due to SiC material's superior electric-field withstanding capability. This smaller die size improves the switching performance significantly but deteriorates the thermal performance of the device packaging. This makes thermal design more challenging when using SiC MOSFETs. When using surface-mount (SM) packaging, printed circuit board (PCB) design plays a key role in the overall thermal design. Understanding the PCB design choices is necessary to maximize the performance of SM SiC MOSFET. This paper investigates several key factors in the thermal design of FR4 PCB to reduce junction temperature (Tj) of surface-mount (SM) SiC MOSFETs in steady-state and overload transient conditions. The factors of interest include heat sinks, copper area per device, and copper thickness. In experiments, doubling PCB copper area can reduce Δ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T_{j}$</tex> by > 40% in steady-state operation, making it the dominant factor. Experiments are performed on a two-layer PCB with a 900 V, 20 mΩ SiC device in D2Pak-7L package. For steady-state performance, doubling PCB copper area reduced the junction temperature rise by > 40%, making it the dominant design factor for steady-state thermal performance. For transient tests, copper thickness is the most critical factor. Junction temperature rise reduced by > 30% when PCB copper thickness is increased from 2 ounces (oz) to 6 oz. Experimental data is provided at various current stress levels for nominal steady-state and overload transient conditions. The findings provide thermal design guidelines of FR4 PCB for SM SiC MOSFETs in various applications.

Printed circuit boards (PCBs) are the essential parts to assemble modern electronic circuits. The PCB design and development process has a direct impact on the system cost and time to market. On average, companies report that PCB represents 31% of the overall product cost. Today's electronic circuits and PCB designs are extremely complex. Multi-level mistakes are inevitable during the design and development stages. Cost reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs. A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity, shortens design to market time, and simplifies the overall supply chain. In order to develop a superior product to fulfill a desired functions, good balance needs to be achieved among competing factors such as performance, cost, form factors, manufacturability, design, system flexibility, and supply chain management (Fig 1). A wireless system is usually comprised of several subsystems performing different functions. For example, a typical handset system includes baseband, transceivers, main and diversity FEM, memories, power management, power amplifiers, antenna switch, duplexer filter, etc. In this day and age, system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution, system level integration at the packaging level may provide benefits such as cost effectiveness, flexibility, and a shorter development cycle. A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package.

Printed Circuit Boards (PCBs) are widely used in most electronic devices. Typically, a PCB design has a set of components that needs to be assembled. In a broad sense, this assembly task involves placing PCB components at designated location on a PCB board; fixing PCB components; and testing the PCB after assembly operation to ensure that it is in proper working order. The stringent requirements of having a higher component density on PCBs, a shorter assembly time, and a more reliable product prompt manufacturers to automate the process of PCB assembly. Frequently, a few placement machines may work together to form an assembly line. Thus, the application of more than one machine for component placement on a PCB presents a line-balancing problem, which is basically concerned with balancing the workload of all the machines in an assembly line. This paper describes the application of a new artificial intelligence technique known as the immune algorithm to PCB component placement as well as the line balancing of PCB assembly line. It also includes an overview of PCB assembly and an outline of the assembly line balancing problem. Two case studies are used to validate the IA engine developed in this work. The details of IA, the IA engine and the case studies are presented.

Channel loss is a dominant factor for the signaling performance of high-speed I/O's. Some platform design guides clearly specify the printed-circuit board (PCB) loss requirement. During the initial design stage for PCB material selection, platform designers would like to have the accurate and efficient insertion loss measurement to meet the channel requirement because the PCB material contributes largely to the platform cost. In this paper, a comprehensive study on PCB design and analysis by different industrial methodologies for insertion loss characterization was conducted. Delta-L 2.0 methodology result is correlated with 2x-Thru results and it is good to utilize this for PCB electrical characterization. The de-embedding structure by 4 inch and 2 inch with handheld probes is validated in the accuracy, efficiency and compact test coupon size, compared with the design with 10 inch and 5 inch by SMA.

Purpose In this paper, analytical modelling of heat distribution along the thickness of different printed circuit board (PCB) substrates is presented according to the 1 D heat transient conduction problem. This paper aims to reveal differences between the substrates and the geometry configurations and elaborate on further application of explicit modelling. Design/methodology/approach Different substrates were considered: classic FR4 and polyimide, ceramics (BeO, Al2O3) and novel biodegradables (polylactic-acid [PLA] and cellulose acetate [CA]). The board thicknesses were given in 0.25 mm steps. Results are calculated for heat transfer coefficients of convection and vapour phase (condensation) soldering. Even heat transfer is assumed on both PCB sides. Findings It was found that temperature distributions along PCB thicknesses are mostly negligible from solder joint formation aspects, and most of the materials can be used in explicit reflow profile modelling. However PLA shows significant temperature differences, pointing to possible modelling imprecisions. It was also shown, that while the difference between midplane and surface temperatures mainly depend on thermal diffusivity, the time to reach solder alloy melting point on the surface depends on volumetric heat capacity. Originality/value Results validate the applicability of explicit heat transfer modelling of PCBs during reflow for different heat transfer methods. The results can be incorporated into more complex simulations and profile predicting algorithms for industrial ovens controlled in the wake of Industry 4.0 directives for better temperature control and ultimately higher soldering quality.

It is necessary for reliability and yield to minimize the number of used vias on nets in printed circuit board (PCB) designs. To our knowledge, the proposed fuzzy-clustering-based algorithm is the first work for a general routing region with multiple-pin nets in k -layer circular topological via minimization ( k -CTVM). In this article, given the topological connections in a set of routing nets and a set of k available layers in a routing plane, first, all the multipin nets can be transformed into a set of two-pin nets by introducing a set of preassigned vias onto the branch points on multipin nets and a conflict graph can be constructed for a final set of two-pin nets. Furthermore, the probabilistic similarity between two connected vertices using the same color can be computed for the constrained vertex-coloring problem with k colors in a conflict graph. Next, based on the definition of the clustering distance between two connected vertices in a conflict graph, fuzzy graph clustering can be developed to obtain a fuzzy matrix on k clusters. Finally, all the given nets can be assigned onto the k available layers by introducing a set of necessary vias on two-pin nets and eliminating the unnecessary preassigned vias on multipin nets. Compared with the combination of Cong's algorithm and an iterative net postassignment, NetInsertion1 , in the k -CTVM problem, the experimental results show that our proposed fuzzy-clustering- based algorithm can use less CPU time to reduce 57.3% of the number of the total used vias for eight tested PCB designs. Compared with the combination of Yan's algorithm and an iterative net postassignment, NetInsertion2 , in the k -CTVM problem, the experimental results show that our proposed fuzzy-clustering-based algorithm can reduce 34.0% of the number of the total used vias for eight tested PCB designs.

Floating, i.e. not locally grounded, printed circuit boards (PCBs) at the end of a long harness and above a large ground plane are common in automotive applications. A problem in modeling such setups is the missing ground reference at the PCB side. In this work, two equivalent circuit models are extracted from PCB design data, one based on a broadband SPICE (BBSPICE) netlist generated from S-parameter simulation and the other obtained by partial element equivalent circuit (PEEC) method. They are compared against measurements results of a demonstrator PCB in above described setup. Investigations include the verification of both modeling approaches with respect to low frequency behavior, broadbandness, sensitivity to PCB circuitry modifications and grounding scheme, as well as model generation effort and simulation times.

This paper describes the design and evaluation of high current toroidal Printed Circuit Board (PCB) embedded inductor applicable for high frequency DC/AC converters (lower than 10MHz). The equivalent circuit model of the inductor is presented and the filtering effectiveness is verified by testing three different geometries with its own characteristics and function through a GaN converter. Besides, the temperature rise analysis is provided for all the prototypes by using finite element methods, and the obtained results are also verified by experiments. The reason behind asymmetric trend of temperature rise for the toroidal PCB embedded inductor is also discussed through both simulation and experiment, and the capability of using a heat sink to lower the temperature increment for different geometries is explained.

Flexible electronics and sensors are a key enabling element for the realization of wearables and geometry adaptive devices needed to follow current trends such as the Internet of things or Industry 4.0. Within this paper, we present a new and flexible packaging platform by the fabrication of an ultra-thin and highly flexible printed circuit board (PCB).The thermoplastic polymer Parylene, which combines a variety of unique properties such as optical transparency, biostability and biocompatibility according to ISO 10993, thermal stability as well as low permeability for gases and water, was used as the base for the new PCB.Particularly, its mechanical properties, especially the absence of intrinsic stresses, as well as its low Young’s modulus and good bendability are advantageous when using Parylene films as a free-standing substrate for flexible applications. The chemical inertness of Parylene against all common acids, bases and solvents ensures its compatibility with established standard microsystem technologies.For the realization of ultra-thin flexible PCBs, Parylene was used as a substrate as well as for the encapsulation and protection layer, respectively. Furthermore, Parylene was the dielectric between the metallic conductive layers. These redistribution layers (RDL) were deposited and patterned by standard microsystem technologies, such as sputtering, lithography and wet chemical etching. Hence, structure sizes of down to 10 µm were successfully realized. Different metals, such as gold, copper, and aluminum were tested for the RDL. Alternatively, printing technologies such as screen printing and aerosol jet printing were successfully demonstrated for the if conductive silver layerse. The electrical connection between the various RDL was of special interest throughout the study and was realized by etching vertical vias through the Parylene using oxygen plasma. Due to the low total thickness of the flexible Parylene PCB of 20 µm or even less, the obtained vias through the Parylene feature an advantageous low aspect ratio. For the contact formation through the vias, different methods were investigated, e. g. sputtering, printing and electrochemical deposition.Finally, the fabricated flexible Parylene PCB were characterized with respect to their bendability and electrical properties. Doing so, the resistivity and capacitance were measured as well as the frequency response between 20 kHz and 500 MHz. Particularly, for frequencies below 1 MHz the realized flexible Parylene PCBs show a good electrical performance.A third function of Parylene with respect to the realization of an ultra-thin and flexible PCB is its usage as a barrier or capping layer. Doing so, new approaches such as embedding electronic or sensor components in the flexible PCB can be enabled. Other integration technologies such as wire bonding, printing or gluing were investigated with respect to their usability for the new flexible PCB as well. Besides, also the direct fabrication of sensors on the Parylene flexible PCB was successfully demonstrated by the realization of a flexible potentiometric pH sensor.The presented new type of ultra-thin PCB is a versatile platform for the realization of flexible electronics, sensors and devices. Due to its biocompatible properties, the flexible Parylene PCB can be used for medical applications but also for the integration of MEMS, chemical sensors and optical components, respectively. Doing so, it enables the realization of smart systems for wearable applications and their integration into light weight constructions. Within this paper, the concept of this new approach, the respected fabrication and integration technologies as well as possible applications are presented in detail. Figure 1

This paper discusses the thermal management challenges presented when using power flip chips on organic laminate structures, and evaluates design variables that would produce the lowest thermal resistance between the die surface and a product housing. Power integrated circuits are often mounted in a package that features design elements for both electrical interconnect and thermal management. One such package is the TO-220. This package allows the electrical interconnect path to be separate from the thermal path by using the center pin as the electrical connection for the drain, and the tab as the thermal management path. When this package is not used, and the die is placed directly on the Printed Circuit Board (PCB) as a flip chip, the electrical and thermal paths come very close in proximity, creating conflicting requirements under the flip chip. This paper addresses these issues and proposes a solution for thermally managing a power flip chip. Included in this paper are basic design options for optimizing the thermal path and how it interacts with electrical interconnect requirements. Specific chip design considerations such as flip chips with two sets of solder bumps for thermal and electrical connection are discussed. Unique PCB technologies including embedded heat-sinks are also evaluated. Detailed evaluations using Finite Element Analysis (FEA) models are shown to determine the optimized design and the interaction between several variables including solder bumps, PCB vias and PCB thickness are discussed. Empirical test results using special thermal test die and various PCB configurations are also presented.

The development of the plastic electronics industry has drawn great interest and inspired technology innovations in a broad area. This has stimulated the rapid development of flexible circuitry manufacturing technologies, including advances in conductive inks, printing technology and most importantly the novel curing technology - laser based curing (or Laser Direct Write). This has the ability to replace the conventional environmentally damaging and time consuming chemical etching method in current Printed Circuit Board (PCB) manufacturing.This work presented in this paper is an investigation into the Nd:YAG laser curing process at the wavelength of 532 nm of particulate silver inks. A mathematical approximation of key physical properties has been developed based on the presented experimental research for use in a finite element model (FEM) simulation. 532 nm has shown benefits in protecting the flexible substrate used from thermal damage, owing to the high transparency of the wavelength through the substrate material. In this paper, liquid-phase particulate silver ink tracks deposited on flexible substrates were irradiated by laser along the track geometry. Repetition of the laser beam scanning was found to produce a smooth and fully cured sample and further reduced the track’s electrical resistivity.The development of the plastic electronics industry has drawn great interest and inspired technology innovations in a broad area. This has stimulated the rapid development of flexible circuitry manufacturing technologies, including advances in conductive inks, printing technology and most importantly the novel curing technology - laser based curing (or Laser Direct Write). This has the ability to replace the conventional environmentally damaging and time consuming chemical etching method in current Printed Circuit Board (PCB) manufacturing.This work presented in this paper is an investigation into the Nd:YAG laser curing process at the wavelength of 532 nm of particulate silver inks. A mathematical approximation of key physical properties has been developed based on the presented experimental research for use in a finite element model (FEM) simulation. 532 nm has shown benefits in protecting the flexible substrate used from thermal damage, owing to the high transparency of the wavelength through the subst...

compatibility (EMC) is an engineering discipline often identified as black magic. This belief exists because the fundamental mechanisms on how radio frequency (RF) energy is developed within a printed circuit board (PCB) is not well understood by practicing engineers. Rigorous mathematical analysis is not required to design a PCB. Using basic EMC theory and converting complex concepts into simple analogies helps engineers understand the mitigation process that deters EMC events from occurring. This user-friendly reference covers a broad spectrum of information never before published, and is as fluid and comprehensive as the first edition. The simplified approach to PCB design and layout is based on real-life experience, training, and knowledge. Printed Circuit Board Techniques for EMC Compliance, Second Edition will help prevent the emission or reception of unwanted RF energy generated by components and interconnects, thus achieving acceptable levels of EMC for electrical equipment. It prepares one for complying with stringent domestic and international regulatory requirements. Also, it teaches how to solve complex problems with a minimal amount of theory and math. Essential topics discussed include: * Introduction to EMC * Interconnects and I/O * PCB basics * Electrostatic discharge protection * Bypassing and decoupling * Backplanes-Ribbon Cables-Daughter Cards * Clock Circuits-Trace Routing-Terminations * Miscellaneous design techniques This rules-driven book-formatted for quick access and cross-reference-is ideal for electrical and EMC engineers, consultants, technicians, and PCB designers regardless of experience or educational background. Sponsored by: IEEE Electromagnetic Compatibility Society

The present paper provides a review of the main concepts and principles involved in mixed PCBs (printed circuit board) design for electronic devices with mixed technologies, i.e. analog, RF (radio frequency) and digital components within the same PCB, such as characteristic impedance, layer stack-up and shielding.

Thermal design of PCBs (Printed Circuit Boards) is important for electronic packages which are intended to be primarily cooled by heat flow into the PCB. Designing the required PCB coverage area through detailed numerical simulations can be computationally expensive. This article presents a quick approach to predict Junction-to-Air thermal resistance of exposed pad packages based on pre-generated detailed thermal simulations and interpolation methodology. The modeling methodology is derived from validated measurements on Quad and Inline packages with different PCB copper coverage areas. Thermal data is pre-generated through parametric simulations conducted with varying package sizes, pad sizes, and PCB copper coverage areas. The interpolation methodology quickly provides a thermal resistance versus copper coverage area curve. The interpolation approach is validated through detailed simulations on cases not included in the pre-generated thermal data. Such a quick prediction capability of temperature rise of exposed pad packages for different PCB copper coverage areas can be a valuable tool for thermal design of PCB layout.

Printed circuit board (PCB) is the main component in almost all electronic devices. The increase in the demand for PCB cause dramatically increases of E-waste. The improper discard practice of printed circuit board (PCB) leads to human health and environmental problems. Although the study had been done to improve the recycling process of E-waste, awareness from various parties needs more effort for this improved recycling process to successfully implement. Therefore, an alternative way by substitute the conventional PCB with the new flexible PCB can help eliminate these issues. The basic design of a flexible PCB consists of a flexible base and conductor. However, a key point during the developing of this new technology is the adhesion between the flexible base and conductor, which thermoplastic polyurethane (TPU) as the base, while silver as the conductor was used throughout this study. This paper presents the effect of temperature in improving adhesion between substrate and silver, and concurrently influence the electrical conductivity of silver conductor. In this study, the characterization of silver and substrate respected to temperature individually analysed, followed by the qualitative adhesion observation between silver and substrate was carried out through cross-cut test according to ASTM D3359-09. The silver was exposed to different curing temperatures exhibit lower sheet resistance when temperature increase. Meanwhile, the substrate exposed to a temperature higher than glass transition (Tg) increases improve the adhesion between silver and substrate.