Improving Code Density with Variable Length Encoding Aware Instruction Scheduling

Effective and efficient modelling and management of hardware resources have always been critical toward generating highly efficient code in optimizing compilers. The instruction templates and dispersal rules of the EPIC architecture add new complexity in managing resource constraints to instruction scheduler. We extended a finite state automaton (FSA) approach to efficiently manage all key resource constraints of an EPIC architecture on-the-fly during instruction scheduling. We have fully integrated the FSA-based resource management into the instruction scheduler in the Open Research Compiler for the EPIC architecture. Our integrated approach shows up to 12% speedup on some SPECint2000 benchmarks and 4.5% speedup on average for all SPECint2000 benchmarks on an Itanium machine when compares to an instruction scheduler with decoupled resource management. In the meantime, the instruction scheduling time of our approach is reduced by 4% on average.


 
 
 Code size is a primary concern in the embedded computing community. Minimizing physical memory requirements reduces total system cost and improves performance and power efficiency. VLIW processors rely on the compiler to statically encode the ILP in the program before its execution, and because of this, code size is larger relative to other processors. In this paper we describe the co-design of compiler optimizations and processor architecture features that have progressively reduced code size across three generations of a VLIW processor.
 
 

Instruction level parallelism has become more and more important in today's microprocessor design. These microprocessors have multiple function units, which can execute more than one instruction at the same machine cycle to enhance the uniprocessor performance. Since the function units are usually pipelined in such microprocessors, branch misprediction penalty tremendously degrades the CPU performance. In order to reduce the branch misprediction penalty, predicated operation has been introduced in such microprocessor design as one of the new architectural features, which allows compilers to remove branches from programs. The compiler converts programs with conditional branch to predicated code on these microprocessors with predicate operation support by using comparison instructions to set up Boolean predicates corresponding to branch conditions. Instructions previously guarded by a branch are guarded by a predicate. Predicates guard execution by either executing or nullifying the instruction according to the predicate's value. In this report we present an algorithm to convert a control flow graph into predicated code. The algorithm shown in this report not only minimizes the number of predicates used for basic blocks in the control flow, but also moves the predicate assignments as early as possible to relax dependence constrains introduced by the if-conversion for the later phases of compiler such as the instruction scheduler and register allocator. The algorithm doesn't simply assign the predicate associated with a basic block to the instructions in the basic block. It assigns the predicate associated with the “farthest” dominator basic block to an instruction, to which the instruction can be speculatively moved without introducing compensation code in the instruction scheduling. An optimization algorithm for if-converted code is discussed in the report as well. The algorithm is specially developed for predicated code optimization, which is different from the traditional optimizations. Common subexpression hoisting and sinking employs flow analysis, that extends the traditional common subexpression elimination technique. This algorithm requires traditional flow analysis information such as dominate and post-dominate relationship. Actually, the algorithm can be generalized on predicated code after if-conversion, which is particularly beneficial for single assignment DAG representation of the predicated code.

Constrained LQR for low-precision data representation

Register allocation and instruction scheduling are often separated due to the complexity of each. But if register allocation is performed before scheduling, it may introduce artificial data precedence, keeping the instruction scheduler from doing its best job. On the other hand, waiting until after scheduling to perform register allocation may produce impossible schedules. In this paper we present a unified approach to instruction scheduling and global (beyond basic blocks) register allocation.

SAD(Sum of Absolute Difference) 알고리즘은 동영상 인코더에서 가장 많은 시간이 소용되는 것으로 잘 알려진 움직임 추정에서 가장 자주 계산이 수행되는 알고리즘으로, 동영상 인코딩 수행시간을 줄이기 위해서 우선적으로 최적화 구현되어야 하는 알고리즘이다. 본 논문에서는 VLIW 기반 고성능 DSP 프로세서에서의 조건 분기를 갖는 SAD 알고리즘의 최적 스케줄링 구현 방법을 제안한다. 제안 방법은 먼저 조건 분기를 갖는 중첩 루프를 VLIW 구조가 제공하는 ILP(Instruction Level Parallelism) 능력을 잘 활용할 수 있도록 충분한 크기의 루프 몸체를 가지며 또한 빨리 루프를 탈출 할 수 있는 조건 분기를 갖는 단일 루프로 변환한 후에, 모듈로 스케줄링 기법을 적용하여 VLIW 기반 프로세서에서 최적화 스케줄링 구현을 한다. 제안된 구현 방안을 TMS320C6713에서 구현하고, 코드 크기 및 수행 시간에 대한 성능 분석을 하였다. 구현된 최적화 SAD 루틴은 코드 크기도 크지 않아 임베디드 응용에 적합하며, 이 SAD 구현을 사용한 H.263 인코더가 그렇지 않은 H.263 인코더보다 훨씬 좋은 성능을 보임을 실험을 통해 확인하였다. SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structured, and few regular loop nests exist. Real world applications in embedded computing contain hot loops with pointers, indirect arrays accesses, function calls, indirect function calls, non constant stride accesses, etc. Consequently, loop transformations for reducing cache misses are impossible to apply, especially at the back-end level. Second, the strides of memory accesses do not appear to be constant at source code level, because of indirect accesses. Hence, usual prefetching techniques are not applicable. Third, embedded VLIW processors are "cheap" products, they have limited hardware dynamic mechanisms compared to high performance processors : no out-of-order execution, reduced memory hierarchies, small direct mapped caches, lower clock frequencies, etc. Consequently, the code optimisations methods must be simple and take care of code size. This article presents a back-end code optimisation for tolerating non-blocking cache effects at the instruction level (not at the loop level). Our method is based on a robust combination of memory pre-loading with data prefetching, allowing us to optimise both regular and irregular applications at the assembly level. Our experiments with mediabench and SPEC2000 benchmarks suites on the ST231 VLIW processor show a positive performance gain (compared to codes generated with -O3 compiler optimisation flag). Our method induces negligible code size growth (less than 3.9 \% in the extreme case).

A basic block in a program is a sequence of consecutive operations, such that control flow enters at the beginning and leaves at the end without internal branches. While basic block scheduling is the simplest non-trivial instruction scheduling problem, it is also the most fundamental and widely used in both software and hardware implementations of instruction scheduling. This chapter introduces basic terminology used in all subsequent chapters and covers a number of different approaches to basic block scheduling.

Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without heroic compiling techniques, most such processors fall far short of their performance goals. Those techniques are largely found in the high-level optimization phase and in the code generation phase; they are also collectively called instruction scheduling. This paper reviews the state of the art in code generation for ILP parallel processors. Modern ILP code generation methods move code across basic block boundaries. These methods grew out of techniques for generating horizontal microcode, so we introduce the problem by describing its history. Most modem approaches can be categorized by the shape of the scheduling region. Some of these regions are loops, and for those techniques known broadly as are used. Software Pipelining techniques are only considered here when there are issues relevant to the region-based techniques presented. The selection of a type of region to use in this process is one of the most controversial questions in code generation; the paper surveys the best known alternatives. The paper then considers two questions: First, given a type of region, how does one pick specific regions of that type in the intermediate code. In conjunction with region selection, we consider region enlargement techniques such as unrolling and branch target expansion. The second question, how does one construct a schedule once regions have been selected, occupies the next section of the paper. Finally, schedule construction using recent, innovative resource modeling based on finite-state automata is then reexamined. The paper includes an extensive bibliography.

An incremental basic block instruction scheduler

Modern compilers are still built using technology that existed decades ago. These include basic algorithms and techniques for lexing, parsing, data-flow analysis, data dependence analysis, vectorization, register allocation, instruction selection, and instruction scheduling. It is high time that we modernize our compiler toolchain. In this talk, I will show the path to the modernization of one important compiler technique -- vectorization. Vectorization was first introduced in the era of Cray vector processors during the 1980's. In modernizing vectorization, I will first show how to use new techniques that better target modern hardware. While vector supercomputers need large vectors, which are only available by parallelizing loops, modern SIMD instructions efficiently work on short vectors. Thus, in 2000, we introduced Superword Level Parallelism (SLP) based vectorization. SLP finds short vector instructions within basic blocks, and by loop unrolling we can convert vector parallelism to SLP. Next, I will show how we can take advantage of the power of modern computers for compilation, by using more accurate but expensive techniques to improve SLP vectorization. Due to the hardware resource constraints of the era, like many other compiler optimizations, SLP implementation was a greedy algorithm. In 2018, we introduced goSLP, which uses integer linear programming to find an optimal instruction packing strategy and achieves 7.58% geomean performance improvement over the LLVM's SLP implementation on SPEC2017fp C/C++ programs. Finally, I will show how to truly modernize a compiler by automatically learning the necessary components of the compiler with Ithemal and Vemal. The optimality of goSLP is under LLVM's simple per instruction additive cost model that fits within the Integer programming framework. However, the actual cost of execution in a modern out-of-order, pipelined, superscalar processor is much more complex. Manually building such cost models as well as manually developing compiler optimizations is costly, tedious, error-prone and is hard to keep up with the architectural changes. Ithemal is the first learnt cost model for predicting the throughput of x86 basic blocks. It not only significantly outperforms (more than halves the error) state-of-the-art analytical hand-written tools like llvm-mca, but also is learnt from data requiring minimal human effort. Vemal is a learnt policy for end-to-end vectorization as opposed to tuning heuristics, which outperforms LLVM's SLP vectorizer. These data-driven techniques can help achieve state-of-the-art results while also reducing the development and maintenance burden of the compiler developer.

The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler phases include instruction scheduling, which maximizes instruction level parallelism (ILP), and register allocation, which minimizes data spills to external memory. If ILP is maximized without considering register constraints, high register pressure may result, leading to increased spill code and reduced run-time performance. In this paper, a new register pressure reduction technique for embedded VLIW processors is presented to control register pressure prior to instruction scheduling and register allocation. By modifying the relative ordering of operations, this technique restructures code to better reduce spills. Our technique has been implemented in Trimaran, an academic VLIW compiler, and evaluated using a series of VLIW benchmarks. Experimental results show that, on average, our algorithm reduces dynamic spills and improves overall cycle counts by 6% for a VLIW architecture with 8 functional units and 32 registers versus previous spill code reduction techniques.

Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for the target processor. Conventionally, these power models are deterministic. However, in reality, there will always be some degree of imprecision involved. For power critical applications, it is desirable to find an optimal schedule which makes sure that the effects of these uncertainties could be minimized. The scheduling algorithm has to be computationally efficient in order to be practical for use in compilers. In this paper, we propose a rule based genetic algorithm to efficiently solve the optimization problem of power-balanced VLIW instruction scheduling with uncertainties in the power consumption model. We theoretically prove our rule-based genetic algorithm can produce as good optimal schedules as the existing algorithms proposed for this problem. Furthermore, its computational efficiency is significantly improved.

The application fields of bytecode virtual machines and Very Long Instruction Word (VLIW) processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to instruction scheduling, which is required in VLIW architectures. While the rewards for dynamic optimization may be high, the trade-offs between optimization benefits and overheads must be fully understood.To this end, we have extended the work of the original JIST project [1], a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor, to include a full implementation of a superblock scheduler. We show the impact of global scheduling on the performance of code compiled with JIST through the experimental study of a set of benchmark programs. We report significant speedups with respect to the local scheduling version of the JIST compiler.

The El'brus-3 and MARS-M represent two recent efforts to address the Soviet Union's high-performance computing needs through original, indigenous development. The El'brus-3 extends very long instruction word (VLIW) concepts to a multiprocessor environment and offers features that increase performance and efficiency and decrease code size for both scientific and general-purpose applications. It incorporates procedure static and globally dynamic instruction scheduling, multiple, simultaneous branch path execution, and iteration frames for executing loops with recurrences and conditional branches. The MARS-M integrates VLIW, data flow, decoupled heterogeneous processors, and hierarchical systems into a unified framework. It also offers a combination of static and dynamic VLIW scheduling. While the viability of these machines has been demonstrated, significant barriers to their production and use remain.