On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors


 
 
 Code size is a primary concern in the embedded computing community. Minimizing physical memory requirements reduces total system cost and improves performance and power efficiency. VLIW processors rely on the compiler to statically encode the ILP in the program before its execution, and because of this, code size is larger relative to other processors. In this paper we describe the co-design of compiler optimizations and processor architecture features that have progressively reduced code size across three generations of a VLIW processor.
 
 

SAD(Sum of Absolute Difference) 알고리즘은 동영상 인코더에서 가장 많은 시간이 소용되는 것으로 잘 알려진 움직임 추정에서 가장 자주 계산이 수행되는 알고리즘으로, 동영상 인코딩 수행시간을 줄이기 위해서 우선적으로 최적화 구현되어야 하는 알고리즘이다. 본 논문에서는 VLIW 기반 고성능 DSP 프로세서에서의 조건 분기를 갖는 SAD 알고리즘의 최적 스케줄링 구현 방법을 제안한다. 제안 방법은 먼저 조건 분기를 갖는 중첩 루프를 VLIW 구조가 제공하는 ILP(Instruction Level Parallelism) 능력을 잘 활용할 수 있도록 충분한 크기의 루프 몸체를 가지며 또한 빨리 루프를 탈출 할 수 있는 조건 분기를 갖는 단일 루프로 변환한 후에, 모듈로 스케줄링 기법을 적용하여 VLIW 기반 프로세서에서 최적화 스케줄링 구현을 한다. 제안된 구현 방안을 TMS320C6713에서 구현하고, 코드 크기 및 수행 시간에 대한 성능 분석을 하였다. 구현된 최적화 SAD 루틴은 코드 크기도 크지 않아 임베디드 응용에 적합하며, 이 SAD 구현을 사용한 H.263 인코더가 그렇지 않은 H.263 인코더보다 훨씬 좋은 성능을 보임을 실험을 통해 확인하였다. SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

Function inlining is a widely known technique that has been adopted in compiler optimization research domain. Inlining functions can eliminate the overhead resulted from function calls, but with inlining, the code size also grows unpredictably; this is not suitable for embedded processors whose memory size is relatively small. In this paper, we introduce a novel function inlining approach using the heuristic rebate_ratio, functions to be inlined are selected according to their rebate_ratios in a descending way. This kind of code optimization operation works at the source code level. Comparing with other algorithms, it is easier to implement. Our target is to get an optimal result of function inlining which can achieve the maximum performance improvement while keeping the code size within a defined limit.

Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to superscalar and VLIW processors for embedded multimedia applications. The comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to /spl times/86 CISC code. The simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.

Variable length encoding can considerably decrease code size in VLIW processors by reducing the number of bits wasted on encoding No Operations(NOPs). A processor may have different instruction templates where different execution slots are implicitly NOPs, but all combinations of NOPs may not be supported by the instruction templates. The efficiency of the NOP encoding can be improved by the compiler trying to place NOPs in such way that the usage of implicit NOPs is maximized. Two different methods of optimizing the use of the implicit NOP slots are evaluated: (a) prioritizing function units that have fewer implicit NOPs associated with them and (b) a post-pass to the instruction scheduler which utilizes the slack of the schedule by rescheduling operations with slack into different instruction words so that the available instruction templates are better utilized. Three different methods for selecting basic blocks to apply FU priorization on are also analyzed: always, always outside inner loops, and only outside inner loops only in basic blocks after testing where it helped to decrease code size. The post-pass optimizer alone saved an average of 2.4 % and a maximum of 10.5 % instruction memory, without performance loss. Prioritizing function units in only those basic blocks where it helped gave the best case instruction memory savings of 10.7 % and average savings of 3.0 % in exchange for an average 0.3 % slowdown. Applying both of the optimizations together gave the best case code size decrease of 12.2 % and an average of 5.4 %, while performance decreased on average by 0.1 %.

This paper presents general software optimization techniques to improve software performance and energy consumption in embedded systems. Software optimization can be categorized into three levels: algorithmic, source code-level. Then these techniques are applied to optimize our tactical message processing software, which is a message encoder-decoder for tactical communication equipped on weapon systems. The optimized software achieved performance increase of about 12%, memory access decrease of 72% and memory usage decrease of 35% over the original software.

HPC systems are widely used for accelerating calculation-intensive irregular applications, e.g., molecular dynamics (MD) simulations, astrophysics applications, and irregular grid applications. As the scalability and complexity of current HPC systems keeps growing, it is difficult to parallelize these applications in an efficient fashion due to irregular communication patterns, load imbalance issues, dynamic characteristics, and many more. This paper presents a fine granular programming scheme, on which programmers are able to implement parallel scientific applications in a fine granular and SPMD (single program multiple data) fashion. Different from current programming models starting from the global data structure, this programming scheme provides a high-level and object-oriented programming interface that supports writing applications by focusing on the finest granular elements and their interactions. Its implementation framework takes care of the implementation details e.g., the data partition, automatic EP aggregation, memory management, and data communication. The experimental results on SuperMUC show that the OOP implementations of multi-body and irregular applications have little overhead compared to the manual implementations using C++ with OpenMP or MPI. However, it improves the programming productivity in terms of the source code size, the coding method, and the implementation difficulty.

The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RS-FDRA), suitable for optimizing compilers targeting embedded VLIW processors. The key difference between RS-FDRA and previous approaches is that our algorithm can handle code size constraints along with latency and resource constraints. This capability enables the exploration of pareto optimal points with respect to code size and performance. RS-FDRA can also minimize the increase in pressure typically incurred by software pipelining. This ability is critical since, the need to insert spill code may result in significant performance degradation. Extensive experimental results are presented demonstrating that the extended set of optimization goals and constraints supported by RS-FDRA enables a thorough compiler-assisted exploration of trade-offs among performance, code size, and register requirements, for time critical segments of embedded software components.

Chapter 6 - Multiprocessor Machines

The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous approaches in that it can effectively handle code size constraints along with latency and resource constraints. Experimental results are presented showing that FDRA's solutions to the traditional software-pipelining problem, which considers latency minimization under resource constraints only, have similar quality to those produced by the best state-of-the-art algorithms. Additionally, it is argued that FDRA's novel ability to explicitly consider code size constraints allows embedded system designers to explore performance vs. code size trade-offs, both unquestionably important figures of merit for embedded software.

During the last 15 years, embedded systems have grown in complexity and performance to rival desktop systems. The architectures of these systems present unique challenges to processor microarchitecture, including instruction encoding and instruction fetch processes. This paper presents new techniques for reducing embedded system code size without reducing functionality. This approach is to extract the pipeline decoder logic for an embedded VLIW processor in software at system development time. The code size reduction is achieved by Huffman compressing or tailor encoding the ISA of the original program. Some interesting results were found. In particular, the degree of compression for the ROM doesn't translate into an improvement in instructions delivered per cycle. Experiments found that when the missprediction penalty of the added Huffman decoder stage was taken into account, a Tailored ISA approach produced higher performance. Methods that compress the entire operation using Huffman encodings, and decompress at ICache hit time still achieved a median performance advantage, while providing higher ROM size savings. All results were generated by an optimizing compiler and tool suite, and presented for an encoding similar to the Intel/HP IA-64 architecture.

Traditional alias analysis is expensive and ineffective for dynamic optimizations. In practice, dynamic optimization systems perform memory optimizations speculatively, and rely on hardware, such as alias registers, to detect memory aliases at runtime. Existing hardware alias detection schemes either cannot scale up to a large number of alias registers or may introduce false positives. Order-based alias detection overcomes the limitations. However, it brings considerable challenges as how software can efficiently manage the alias register queue and impose restrictions on optimizations. In this paper, we present SMARQ, a Software-Managed Alias Register Queue, which manages the alias register queue efficiently and supports more aggressive speculative optimizations. We conducted experiments with a dynamic optimization system on a VLIW processor that has 64 alias registers. The experiments on a suite of SPECFP2000 benchmarks show that SMARQ improves the overall performance by 39% as compared to the case without hardware alias detection. By scaling up to a large number (from 16 to 64) of alias registers, SMARQ improves performance by 10%. Compared to a technique with false positives (similar to Itanium), SMARQ improves performance by 13%. To reduce the chance of alias register overflow, the novel alias register allocation algorithm in SMARQ reduces the alias register working set by 74% as compared to a straightforward alias register allocation based on program order.

The main objective of coding theory is to find codes with efficient encoding and decoding techniques and the greatest possible value of distance for a given code length, code size, and code alphabet cardinality. Various distances like Hamming distances, symbol-pair distances, etc., have been established and investigated in coding theory to analyse a code’s error-detecting and error-correcting capabilities with respect to various communication channels. A maximum distance separable code (MDS code) is a code that meets the Singleton bound. The MDS codes have the greatest error correcting capability. When the length and size of the codes are fixed, an MDS code has the largest distance. As a result, nowadays, researching and discovering MDS codes with respect to various distances is a hot topic in coding theory. In the theory of error-correcting codes, constacyclic codes over finite fields play a crucial role. Constacyclic codes, moreover, have many real-world applications. Shift registers can effectively encode and decode these codes because they have rich algebraic structures. They also offer excellent error-correction capabilities. All of this clarifies their chosen engineering role. In this monograph, we determine the multi-symbol distances of various classes of repeated-root constacyclic codes over some classes of finite commutative chain rings and investigate various classes of non-trivial MDS codes using these multi-symbol distance distributions.

Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by increasing the parallelism among successive loop iterations. Traditionally, retiming has been applied at instruction level to reduce cycle period for single loops. While multi-dimensional (MD) retiming can explore the outer loop parallelism, it introduces large overheads in loop index generation and code size due to loop transformation. In this paper, we propose a novel approach, that combines iterational retiming with instructional retiming to satisfy any given timing constraint by achieving full parallelism for iterations in a partition with minimal code size. The experimental results show that combining iterational retiming and instructional retiming, we can achieve 37% code size reduction comparing to applying iteration retiming alone.

Existing generic benchmarks for accelerators (e.g. Parboil and Rodinia) have focused on high performance computing (HPC) applications which have limited control flows and data irregularity. Previous available graph analytics benchmark suites include straightforward implemented workloads which do not employ up-to-date optimization techniques and thus have quite different behaviors from real-world applications. This paper first briefly presents and characterizes the Graph Analytics Repository for Designing Next-generation Accelerators (GARDENIA) 1, which is a benchmark suite for studies of irregular algorithms on various massively parallel accelerators. It includes emerging irregular big-data and machine learning applications, in which mimic massively multithreaded programs deployed on not only datacenters but also hand-on devices. Then we characterize Nvidia GPU with GARDENIA, covering a wide spectrum of metrics such as parallelization, cache locality, off-chip traffic and irregularity. Based on the characterization on Nvidia GPU, we unveil the performance bottlenecks of the current mainstream accelerator and give architectural insights for building high performance and energy-efficient domain-specific accelerators for graph applications.