Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structured, and few regular loop nests exist. Real world applications in embedded computing contain hot loops with pointers, indirect arrays accesses, function calls, indirect function calls, non constant stride accesses, etc. Consequently, loop transformations for reducing cache misses are impossible to apply, especially at the back-end level. Second, the strides of memory accesses do not appear to be constant at source code level, because of indirect accesses. Hence, usual prefetching techniques are not applicable. Third, embedded VLIW processors are "cheap" products, they have limited hardware dynamic mechanisms compared to high performance processors : no out-of-order execution, reduced memory hierarchies, small direct mapped caches, lower clock frequencies, etc. Consequently, the code optimisations methods must be simple and take care of code size. This article presents a back-end code optimisation for tolerating non-blocking cache effects at the instruction level (not at the loop level). Our method is based on a robust combination of memory pre-loading with data prefetching, allowing us to optimise both regular and irregular applications at the assembly level. Our experiments with mediabench and SPEC2000 benchmarks suites on the ST231 VLIW processor show a positive performance gain (compared to codes generated with -O3 compiler optimisation flag). Our method induces negligible code size growth (less than 3.9 \% in the extreme case).

We have developed a superscalar RISC processor for the super technical server HITACHI SR8000. The processor includes architectural features specialized in scientific applications, in which massive amounts of data in the main memory must be processed. These features are a slide-windowed-registers scheme and a simultaneous execution of up to 16 prefetch instructions. The slide-windowed-registers scheme enables instructions of the processor to access any of 160 floating point registers (FPRs). The execution mechanism for prefetch instructions produces high efficiency of the out-of-order superscalar processor despite the long latency of the main memory. A logic simulation showed that the performance of the processor reaches over 3 floating-point operations per cycle and the memory throughput of over 12 bytes per cycle.

Short-vector SIMD and DSP instructions are popular extensions to common Isas. These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialised compiler support. To enable the programmer to explicitly request the use of such an instruction, many C compilers provide platform-specific intrinsic functions, whose implementation is handled specially by the compiler. The use of such intrinsics, however, inevitably results in non-portable code. In this paper we develop a novel methodology for retargeting such non-portable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform. We employ a description language to specify the signature and semantics of intrinsics and perform graph-based pattern matching and high-level code transformations to derive optimised implementations exploiting the target's intrinsics, wherever possible. We demonstrate the effectiveness of our new methodology, implemented in the FREE RIDER tool, by automatically retargeting benchmarks derived from OpenCV samples and a complex embedded application optimised to run on an Arm Cortex-M4 to an Intel Edison module with Sse4.2 instructions. We achieve a speedup of up to 3.73 over a plain C baseline, and on average 96.0% of the speedup of manually ported and optimised versions of the benchmarks.

In the multi-output high-voltage isolated power supply for solid-state switches, LCL resonant network is used to obtain the constant current source on the bus, and the bus current is independent of the load. Therefore, the secondary side of the toroidal transformer needs to use the current input voltage regulator circuit. When the input is a current source instead of a voltage source, the traditional voltage regulator circuit is no longer applicable. Therefore, this paper focuses on the study of dc voltage regulated circuit with current source input. Compared with the traditional linear regulated power supply, switching power supply has the advantages of high efficiency, large output power, small size, light weight and low cost. In this paper, pulse width modulation (PWM) technology is used to control the switching on and off, and UC3843 is used to design a switch type regulated power supply with small size, simple circuit, adjustable output and over voltage protection function. Tina-TI software was used for simulation analysis, and the main circuit and control circuit were built. The current source of 1.25A and 40kHz output by the secondary side of the toroidal transformer is converted into a stable 10V DC voltage source, which verified the correctness of the design. Tina-TI software can be used to analyze and design power supply with different requirements, improve power efficiency, reduce design complexity, and thus shorten development cycles.

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geometry processing of 3D graphics on the host CPU and have specialized hardware handle the rendering task. In this paper, we analyze microarchitecture and SIMD instruction set enhancements to a RISC superscalar processor for exploiting instruction level parallelism (ILP) in geometry processing for 3D computer graphics. Our results show that 3D geometry processing has inherent parallelism. When ignoring cycle time effects, an 8-issue processor can achieve up to 60% performance improvement over a 4-issue. However, certain application attributes can hinder the exploitation of ILP on a superscalar processor. Adding SIMD operations improves performance from 8% to 28% on a 4-issue processor that can issue at most 2 floating-point operations. If processor cycle time scales with the number of ports to the register file, doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architecture configurations that we examine (the most aggressive configuration is an 8-issue processor with SIMD instructions).

The JCSAT 9 Communications Satellite, developed by Lockheed Martin Commercial Space Systems using an A2100 [1] spacecraft, will use an on-orbit configurable Frequency Generation Unit (FGU) that is SEU hard and total dose tolerant. The spacecraft is due for launch in 2005. The FGU design [2] illustrates the principles and benefits of a single loop synthesizer generating low noise and multiple local oscillators for various frequency (up/down) converters in the payload. Nineteen phase-locked loops are configured to provide coherent, multiple, and redundant C and L band local oscillator frequencies by combining digital, analog and microwave concepts to achieve small size, low mass, low DC power consumption, low phase noise, and spectral purity.

This research explores the design and implementa- tion of an image and video processing platform using recon- figurable FPGA technology. With the increasing demand for real- time, high-performance multimedia processing in modern applications, a flexible and efficient solution is essential. The project utilizes an FPGA-based platform to handle image and video data processing through edge detection, image scaling, and real-time motion detection techniques. By integrating custom- built hardware components, this study aims to provide a low- power, high-throughput solution that meets the requirements of both image and video processing tasks. Materials and methods involved using Xilinx Virtex-II Pro FPGA for hardware imple- mentation, alongside embedded memory processors and multi- functional design elements such as zoom-in/out utilities. The system was evaluated through several experimental procedures, using various image and video datasets, to measure performance in terms of speed, resource utilization, and power consumption. Results indicated that the system achieved notable improvements in terms of efficiency, utilizing 25% of logic resources, 55% of on- chip memory, and 180mW of power. The discussion focuses on the adaptability of FPGA-based systems in meeting the diverse needs of multimedia processing, emphasizing scalability and low power consumption. In conclusion, the reconfigurable FPGA platform provides a versatile and efficient environment for image and video processing. The system’s resource efficiency, scalability, and potential for further enhancements make it a promising candidate for future multimedia applications. Keywords-Reconfigurable FPGA Architecture, Video and Image Processing, Edge Detection, Image Rescaling.

This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.

The state-of-the-art prosthetic devices have been successfully approved as critical approach to provide at least partial reconstruction for physiological diseases by replacing a damaged tissue or organ. Invariably, they are always aspired to have lower power consumption despite the battery or the battery-less implementation. This paper presents an energy-aware baseband circuitry concerned about the next-generation multi-channel prostheses especially for the retinal implant in which an inductive-coil link is preferred to fulfill the need of power delivery for providing safer tissue-machine interfaces in the intraocular environment. The extended lifetime for those of the battery-dependent implants can be also achieved by adopting such a power-efficient scheme. The proposed system is a 16-channel-based on-electrode multiplexing design, which can deal with up to 40 frame/sec with 240 stimulus channels in mode I and 3 times the resolution at the same frame rate in mode II under a carrier frequency of 2 MHz. A prototypical chip was implemented in a 0.18mum CMOS process and the experiment has also been carried out as proof of concept.

SAD(Sum of Absolute Difference) 알고리즘은 동영상 인코더에서 가장 많은 시간이 소용되는 것으로 잘 알려진 움직임 추정에서 가장 자주 계산이 수행되는 알고리즘으로, 동영상 인코딩 수행시간을 줄이기 위해서 우선적으로 최적화 구현되어야 하는 알고리즘이다. 본 논문에서는 VLIW 기반 고성능 DSP 프로세서에서의 조건 분기를 갖는 SAD 알고리즘의 최적 스케줄링 구현 방법을 제안한다. 제안 방법은 먼저 조건 분기를 갖는 중첩 루프를 VLIW 구조가 제공하는 ILP(Instruction Level Parallelism) 능력을 잘 활용할 수 있도록 충분한 크기의 루프 몸체를 가지며 또한 빨리 루프를 탈출 할 수 있는 조건 분기를 갖는 단일 루프로 변환한 후에, 모듈로 스케줄링 기법을 적용하여 VLIW 기반 프로세서에서 최적화 스케줄링 구현을 한다. 제안된 구현 방안을 TMS320C6713에서 구현하고, 코드 크기 및 수행 시간에 대한 성능 분석을 하였다. 구현된 최적화 SAD 루틴은 코드 크기도 크지 않아 임베디드 응용에 적합하며, 이 SAD 구현을 사용한 H.263 인코더가 그렇지 않은 H.263 인코더보다 훨씬 좋은 성능을 보임을 실험을 통해 확인하였다. SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

We design a cryptographic transistor (cryptoristor)-based true random number generator (tRNG) with low power consumption and small footprint. This is the first attempt to use irregular and unpredictable operation-induced randomness of a cryptoristor as an entropy source. To extract discrete random numbers with a binary code from the cryptoristor, we developed a noise-coupling analog-to-digital converter. This converter not only converts analog signals to digital random bits but also improves the randomness of the entropy source with low power consumption. The randomness of the cryptoristor is attributed to the random carrier multiplications with the creation and stochastic carrier escape as destruction, which occurs iteratively as long as the input current is fed. The cryptoristor-based tRNG passed 15 randomness test suites of NIST Special Publication 800-22. It is robust to iterative operational stresses and to ambient temperature changes, making it an attractive option for hardware-based security solutions in the Internet of Things due to its low power consumption and small size.

Table lookups are one of the most frequently-used operations in symmetric key ciphers. Particularly in the newer algorithms such as the advanced encryption standard (AES), we frequently find that the greatest fraction of the execution time is spent during table lookups, varying between 34% and 72% for the five representative ciphers we consider: AES, Blowfish, Twofish, MARS, and RC4. In order to accelerate and parallelize these table lookups, we describe a new parallel table lookup (ptlu) instruction. Our synthesis results indicate that such an instruction can be added to a basic RISC processor with no cycle time impact. We compare the performance of the ptlu instruction with the speedups available through more conventional architectural techniques such as multiple-issue execution. We find that the performance benefits of using the ptlu instruction can be far higher than increasing the number of instructions executed per cycle in superscalar or VLIW processors.

This paper describes a purely software-based approach to handle permanent faults in the data path of a statically scheduled superscalar processor architecture; e.g. a VLIW processor. This approach does not need any hardware in the processor core itself to reconfigure the data path. Rather the reconfiguration is done in software by modifying the binary code in the program memory of the processor. By this, the usage of a faulty component in the data path can be avoided during the execution of the program. The modification of the program is carried out by a repair routine that is executed by the faulty processor itself. It is shown that this is possible even if there is a fault in the data path. The modification of the binary code takes place immediately after a software-based self-test. Both, the self-test and the modification are carried out immediately after the start-up of the system. Thus, the detection and repair of a fault can happen in the field. Furthermore, the compiler must generate the program in a special way in order to guarantee that the binary code can be modified under all specified fault situations. A simple scheduling algorithm that produces such fault-tolerant binary code is presented, too.

Embedded video surveillance has become a large market as the number of installed cameras around us can show. At the same time, video compression technique has been rapidly developed in recent years. As a new generation of video coding compression standard, extensive attention has been given to H.264/AVC. On the other hand, because of good cost-effective and low-power consumption, DSP is widely used in the fields of embedded system and multimedia processing. There are needs for embedded video surveillance that can make use of the video compression technique in more efficiency security systems. In this paper, a scheme of design and implementation about video surveillance system based on H.264/AVC is designed and described. It is built on ADSP-BF561, with a wide range of peripheral interface, to achieve several functions, such as video compression, data stream control, network transmission, PTZ and so on. The experimental results indicate that the stability and other expected features of system, including Real-time surveillance video encoding, can be ensured.