A Fully Integrated Energy-Aware Baseband Circuitry for Next-Generation Retinal Implants

In this paper, an integrated system to control and manage a state-of-the-art industrial computer numerical control (CNC) machine (Studer S33) using a commercially available tablet (Samsung Galaxy Tablet S2) is presented as a proof of concept (PoC) for the ubiquitous control of industrial machines. As a PoC, the proposed system provides useful insights to support the further development of full-fledged systems for Industrial Internet of Things (IIoT) applications. The proposed system allows for the quasi-decentralisation of the control architecture of conventional programmable logic controller (PLC)-based industrial control systems (ICSs) through data and information exchange over the transmission control protocol and the internet protocol (TCP/IP) suite using multiple agents. Based on the TCP/IP suite, a network device (Samsung Galaxy Tablet S2) and a process field net (PROFINET) device (Siemens Simatic S7-1200) are interfaced using a single-board computer (Raspberry Pi 4). An override system mainly comprising emergency stop and acknowledge buttons is also configured using the single-board computer. The input signals from the override system are transmitted to the PROFINET device (i.e., the industrial control unit (ICU)) over TCP/IP. A fully functional working prototype is realised as a PoC for an integrated system designated for the wireless and ubiquitous control of the CNC machine. The working prototype as an entity mainly comprises a mobile (handheld) touch-sensitive human-machine interface (HMI), a shielded single-board computer, and an override system, all fitted into a compact case with physical dimensions of 300 mm by 180 mm by 175 mm. To avert potential cyber attacks or threats to a reasonable extent and to guarantee the security of the PoC, a multi-factor authentication (MFA) including an administrative password and an IP address is implemented to control the access to the web-based ubiquitous HMI proffered by the PoC.

Modern telecommunication networks are quickly evolving from passive content use to an evolutionary and much more participative social model that demands huge capacity, low power consumption, and low cost. Wavelength-division-multiplexing passive optical network (WDM PON) represents one of the current solutions to meet different network requirements. Nevertheless, in order to fully exploit the potential of WDM PON, unbundling issues still require a more efficient management, specially when the network connections get higher, to achieve high flexibility, scalability, minimum hiring together with low power consumption and low cost. Here, unbundling in WDM PON is handled in optical domain in order to exploit the higher bandwidth optics can offer with respect to electronics, avoiding high power consuming due to optical-electrical-optical (OEO) conversions. The use of photonic signal processing enables not only high bit rate but also scalability, easy reconfigurability, modularity, minimum number of fiber links, and “pay as you grow” strategy implementation. An innovative architecture based on WDM/time-division-multiplexing conversion is proposed, and all required all-optical subsystems are experimentally demonstrated, as proof of concept, exploiting nonlinear optical fiber. Power penalty lower than 3 dB is verified for each optical block. Power requirements for each subsystem are also reported. Moreover, the use of new integrated technologies can strongly reduce power consumption footprint and implementations cost.

Infrared focal plane array (IRFPA) with digital read out interface is a key sign of the third generation IRFPA, which plays an important role in the reliability and miniaturization of infrared systems. A readout integrated circuit (ROIC) of IRFPA with digital readout interface based on dual ramp single slope (DRSS) analog to digital converter (ADC) architecture is presented in the paper. The design is realized using shared ADCs in column-wise and these ADCs are consisted of simplified DRSS architecture and shared units. Sample, conversion and readout are proceeded simultaneously in order to adapt large scale and high readout frame rate application. This circuit also shows many advantages, including small area and low power consumption. Simulation result shows that this architecture can be expand to 320×256 pixel array with a frame rate of 100 frames per second or a larger size whit lower frame rate, the quantized resolution of this circuit is 12 bit, and the analog power consumption is only 17μw per ADC.

An ultra-high-speed computational CMOS image sensor with a burst frame rate of 303 megaframes per second, which is the fastest among the solid-state image sensors, to our knowledge, is demonstrated. This image sensor is compatible with ordinary single-aperture lenses and can operate in dual modes, such as single-event filming mode or multi-exposure imaging mode, by reconfiguring the number of exposure cycles. To realize this frame rate, the charge modulator drivers were adequately designed to suppress the peak driving current taking advantage of the operational constraint of the multi-tap charge modulator. The pixel array is composed of macropixels with 2 × 2 4-tap subpixels. Because temporal compressive sensing is performed in the charge domain without any analog circuit, ultrafast frame rates, small pixel size, low noise, and low power consumption are achieved. In the experiments, single-event imaging of plasma emission in laser processing and multi-exposure transient imaging of light reflections to extend the depth range and to decompose multiple reflections for time-of-flight (TOF) depth imaging with a compression ratio of 8× were demonstrated. Time-resolved images similar to those obtained by the direct-type TOF were reproduced in a single shot, while the charge modulator for the indirect TOF was utilized.

Automatic lip-reading (ALR) aims to recognize words using visual information from the speaker's lip movements. In this work, we introduce a novel type of sensing device, event cameras, for the task of ALR. Event cameras have both technical and application advantages over conventional cameras for the ALR task because they have higher temporal resolution, less redundant visual information, and lower power consumption. To recognize words from the event data, we propose a novel Multi-grained Spatio-Temporal Features Perceived Network (MSTP) to perceive fine-grained spatio-temporal features from microsecond time-resolved event data. Specifically, a multi-branch network architecture is designed, in which different grained spatio-temporal features are learned by operating at different frame rates. The branch operating on the low frame rate can perceive spatial complete but temporal coarse features. While the branch operating on the high frame rate can perceive spatial coarse but temporal refinement features. And a message flow module is devised to integrate the features from different branches, leading to perceiving more discriminative spatio-temporal features. In addition, we present the first event-based lip-reading dataset (DVS-Lip) captured by the event camera. Experimental results demonstrated the superiority of the proposed model compared to the state-of-the-art event-based action recognition models and video-based lip-reading models.

Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to superscalar and VLIW processors for embedded multimedia applications. The comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to /spl times/86 CISC code. The simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.

This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.

This paper presents a cost effective solution in optimizing the performance of mass-produced hearing aids for faithful reproduction of sound with low power consumption that prolongs battery life. The dithering scheme is suitable for implementation on various small consumer healthcare devices including hearing aids and personal sound amplifying devices offering improved sound quality with enhanced performance in tone, smoothness and dynamic range. The audio system is found to improve sound quality without dither added to the incoming audio signal.

Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems. In this paper, a monolithic low-power digitally programmable VGA with 75 dB of gain range is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor and tuning the resistors in the common-mode feedback circuitry. The complete VGA consists of three gain stages. As a proof of concept, a 24 dB single-gain stage with 2 dB gain steps is fabricated in a 0.18 ?m CMOS technology. The prototype chip is tested, and measurement results are obtained. Based on these results, the gain stage is redesigned to optimize its performance, and a three-stage 75 dB VGA is designed and simulated. Each stage has a digitally tunable gain range of 25 dB. The overall gain can be varied from ?15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz, and the gain error is less than 0.3 dB. The overall VGA draws 6.5mA from a 1.8V power supply. The noise figure of the system at maximum gain is 12.5 dB, and the third-order intermodulation intercept point (IIP3) at minimum gain is 14.4 dBm.

Artificial vision: needs, functioning, and testing of a retinal electronic prosthesis

The Internet of things is often used on researches analyzing and estimating human behavior and tracking their exact locations through mobile terminals. In particular, localization through the use of IoT is highly effective for watching over seniors, searching a missing child or detecting risky incidents. In this paper, we propose a hybrid system of localization that can be used as an accurate monitoring device for regular use and as a localization device with low power consumption and a long span operation for emergency use. The low power consumption is realized by switching to the system operated on Bluetooth Low Energy. As a result of experiments with actual machines, our proposed system could localize the area of a terminal located within 5 m distance with 100% accuracy. Moreover, its correct position can be identified with 84.2% accuracy by using the finger print method.

A BIMOS-based 2T1C analogue spiking neuron circuit integrated in 28 nm FD-SOI technology for neuromorphic application

Background: Significant progress toward the recovery of useful vision in blind patients with severe degenerative retinal diseases caused by photoreceptor death has been achieved with the development of visual prostheses that stimulate the retina electrically. However, currently used prostheses do not provide feedback about the retinal activity before and upon stimulation and do not adjust to changes during the remodeling processes in the retina. Both features are desirable to improve the efficiency of the electrical stimulation (ES) therapy offered by these devices. Accordingly, devices that not only enable ES but at the same time provide information about the retinal activity are beneficial. Given the above, a bidirectional communication strategy, in which inner retinal cells are stimulated and the output neurons of the retina, the ganglion cells, are recorded using penetrating microelectrode arrays (MEAs) is proposed.Methods: Custom-made penetrating MEAs with four silicon-based shanks, each one with three or four iridium oxide electrodes specifically designed to match retinal dimensions were used to record the activity of light-adapted wildtype mice retinas and degenerated retinas from rd10 mice in vitro. In addition, responses to high potassium concentration and to light stimulation in wildtype retinas were examined. Furthermore, voltage-controlled ES was performed.Results: The spiking activity of retinal ganglion cells (RGCs) was recorded at different depths of penetration inside the retina. Physiological responses during an increase of the extracellular potassium concentration and phasic and tonic responses during light stimulation were captured. Moreover, pathologic rhythmic activity was recorded from degenerated retinas. Finally, ES of the inner retina and simultaneous recording of the activity of RGCs was accomplished.Conclusion: The access to different layers of the retina with penetrating electrodes while recording at the same time the spiking activity of RGCs broadens the use and the field of action of multi-shank and multi-site penetrating MEAs for retinal applications. It enables a bidirectional strategy to stimulate inner retinal cells electrically and to record from the spiking RGCs simultaneously (BiMEA). This opens the possibility of a feedback loop system to acknowledge the success of ES carried out by retinal prostheses.

Security-by-construction in web applications development via database annotations

Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.