Integrated Power and Clock Distribution Network

The impedance characteristics of a power distribution system are analyzed in the previous chapter based on a one-dimensional circuit model. While useful for understanding the principles of the overall operation of a power distribution system, a one-dimensional model is not useful in describing the distribution of power and ground across a circuit die. The size of an integrated circuit is usually considerably greater than the wavelength of the signals in the power distribution network. Furthermore, the power consumption of on-chip circuitry (and, consequently, the current drawn from the power distribution network) varies across the die area. The voltage across the on-chip power and ground distribution networks is therefore non-uniform. It is therefore necessary to consider the two-dimensional structure of the on-chip power distribution network to ensure that target performance characteristics of a power distribution system are satisfied. The on-chip power distribution network should also be considered in the context of a die-package system as the properties of the die-package interface significantly affect the constraints imposed on the electrical characteristics of the on-chip power distribution network.

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.

Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the operating temperature of 3D ICs. In addition, designers use a highly complex hierarchical power distribution network in conjunction with decoupling capacitors to deliver currents. However, these thermal and power/ground interconnects together with those used for signal delivery compete with each other for routing resources including various types of Through-Silicon-Vias (TSVs). This paper presents the first work on routing with these multi-functional interconnects in 3D: signal, thermal, and power distribution networks. We demonstrate how to consider various physical, electrical, and thermo-mechanical requirements of these multi-functional interconnects to successfully complete routing while addressing various reliability concerns.

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

Power distribution (PD) networks have many laterals and load taps. Accurate fault locating in PD systems causes to improve reliability indices and its efficiency. In this paper, a new combined method is proposed for locating single phase fault to earth in PD networks. In this article, an impedance based fault-location algorithm is used to find the possible fault locations. Then the new method is proposed for determining the faulty section using voltage sag matching algorithm. In this method, after occurring single phase fault to ground, the possible locations of fault are determined using the impedance based fault-location algorithm. The same fault is simulated in possible locations, separately. Then the voltage at the beginning of feeder is saved and the amplitude and angle of the voltage differences are determined and online data bank is generated. This data bank is compared with the obtained and recorded amplitude and angle of the voltage differences (at the beginning of feeder) for actual fault. The real location of fault is determined by the matching value of each possible fault location.

Resonant clocking is an attractive alternative to conventional clock distribution due to its significant potential for reducing clocking power. Typically, resonant clock systems rely on sinusoidal clock signals to synchronize flip-flops. Understanding clock skew and power is particularly important in these systems, because unlike their conventional counterparts, resonant clock networks do not use any buffers. We have performed a simulation study of clock skew and power in resonant H-shape clock distribution networks with sinusoidal waveforms. Focusing on the impact of width, spacing, and loading on clock skew, our study suggests practical design guidelines for low-skew resonant clocking. Our results show that compared to conventional clocking, properly designed resonant clocking yields comparable or better skew. Furthermore, simultaneous improvements in skew and power of resonant clock are possible through width scaling. Our experiments also confirm the theoretical prediction that energy dissipation in resonant clock networks scales with RC/T, where RC is the load of the network, and T is the clock period.

With an increasing deployment of plug-in electric vehicles, evaluating and mitigating the impacts of additional electrical loads created by these vehicles on power distribution grids become more important. This paper explores the use of prices of electricity at public charging stations as an instrument, in couple of road pricing, to better manage both power distribution and urban transportation networks. More specifically, a multi-class combined distribution and assignment model is formulated to capture the spatial distribution of plug-in electric vehicles across the transportation network and estimate the electrical loads they impose on the power distribution network. Power flow equations are subsequently solved to estimate real power losses. Prices of electricity at public charging stations and road tolls are then optimized to minimize both real power losses in the distribution grid and total travel time in the urban transportation network. The pricing model is formulated as a mathematical program with complementarity constraints and solved by a manifold suboptimization algorithm and a pattern search method. Numerical examples are presented to demonstrate the proposed model and solution algorithms.

Chapter 10 - Case Study: Clock Distribution Networks for 3-D ICs

The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.

Power losses and voltage deviations in distribution power networks (DPNs) are high since they carry more power demand than transmission power networks. Also, voltage deviation beyond the allowable range causes voltage stability problems in the DPN. The power loss (PL) in the DPN should be kept at the minimum level for the economic operation of the electric grid. Integrating distributed generation (DG) in appropriate sites of the power networks can minimize the power losses and voltage drops. An integrated optimization approach is proposed in this paper, by combining an analytical and metaheuristic algorithm to optimize the placement and sizing of multiple DGs. The active power loss sensitivity (APLS) index is an analytical mathematical computation approach used to identify the optimal bus locations for DG placement. The modified ant lion optimization (MALO) algorithm is applied to optimize the ratings of the DG systems. The MALO algorithm is proposed by adopting the Lévy flights (LF) pattern in the random walk process (RWP). LF representation of RWPs enhances the exploration phase of the ALO algorithm and helps to obtain the near-optimal solution. The proposed integrated approach optimizes multiple units of photovoltaic (PV) and wind turbine (WT) units to minimize the multi-objective function, including AP loss and voltage deviation (VD) minimizations. The effectiveness of the proposed integrated approach is validated on the IEEE 69-bus, 85-bus, and 118-bus radial DPNs. Besides, the simulation study is extended for ant lion optimization (ALO), BAT, and artificial bee colony (ABC) algorithms-based techniques. The integrated approach has reduced the total AP loss of the IEEE 69-bus and 85-bus radial DPN from 225 kW to 70.51 kW and 316.12 kW to 162.80 kW, respectively, for the optimized three PV DG units allocation. Likewise, the total AP loss of the 118-bus radial DPN is cut down from 1296.3 kW to 432.3 kW after the optimized five PV DG units allocation. Meanwhile, the total AP LOSS of the 69-bus, 85-bus, and 118-bus radial DPNs is reduced to 4.78 kW, 53.87 kW, and 112.2 kW, respectively, after the optimized WT DG allocation. Additionally, the optimized inclusion of multiple DG units significantly minimized the VD of the DPNs. The minimum VD of the 69-bus, 85-bus, and 118-bus test systems is reduced from 0.0908 p.u., 0.1297 p.u., and 0.1312 p.u. to 0.0174 p.u., 0.0384 p.u., and 0.0201 p.u., respectively, for the multiple PV unit allocations. Similarly, the minimum VDs of the 69-bus, 85-bus, and 118-bus radial DPNs are minimized to 0.0048 p.u., 0.0190 p.u., and 0.0093 p.u., respectively, following the multiple WT DG unit allocations. The simulation findings of the APLS-MALO integrated approach are related to the various optimization techniques. The comparative study reveals that the proposed integrated approach gives a more effective and efficient solution than ALO, BAT, ABC, and other optimization techniques. Finally, the simulation findings of the APLS-MALO integrated technique are verified via the calculation of conventional statistical metrics and the conduction of a non-parametric Wilcoxon test.

This paper discusses how to perform online integrity checking for a clock system spanning all over a heterogeneously integrated IC. A clock system in this work is assumed to consist of two major components - (1) the Delay-Locked Loop (DLL), commonly used for module-to-module clock synchronization, and (2) the clock distribution network (with clock buffers and interconnects). For the DLL part, we incorporate a “phase error monitoring scheme”, which is able to detect abnormal safety hazard, e.g., an instantaneous power glitch. For the clock distribution network, we incorporate a periodic self-test scheme featuring a “special short-pulse driven flush test procedure” to detect any worsening Clock Delay Fault (CDF). The proposed method can help identify a failure threat before it strikes havoc. Post-layout simulation results are presented to demonstrate the effectiveness of the proposed schemes.

EVs are recognized as distributed loads and power sources with random motion characteristics in the power distribution networks (PDN); therefore, they serve as connecting points for the distribution network and transportation network (PDN-TN), and have significant impact on the stability and reliability of the routine operation of the coupled networks. In order to guarantee the safe operation of PDN-TN, it is necessary to evaluate the reliability of this coupled network. In this paper, the trip chaining theory is applied to describe the travel plan of EVs, and semi-dynamic flow allocation (SDTA) method is adopted to propose a simulation calculation method of energy flow between two networks based on user equalization (UE) criterion. The new reliability evaluation index for energy flow between the coupled networks is further proposed to better evaluate the reliability. Taking into account the daily trip characteristics of EVs, vehicles types, and charging modes, a coupled network reliability evaluation method based on sequential Monte Carlo simulation is put forward. Finally, the practicability of the proposed method is verified by an IEEE-RBTS BUS-6 test system and a 12-node transportation network.

The rapid adoption of electric vehicles (EVs) is driving increased charging demand, intensifying the interdependence between power distribution and transportation networks (PTNs). The main challenge in coordinating the EV routing and charging management within the PTN lies in the intractable nonlinear relationship between electricity price signals in the power distribution network (PN) and EV charging and routing behaviors in the transportation network (TN). Therefore, this paper proposes a novel constraint learning approach using XGBoost to solve the nontrivial bilevel optimization problem of vehicle charging within the PTN. XGBoost is first employed to capture the complex relationship between charging prices and optimal charging demand, leveraging its strong approximation capability to construct a tree-based surrogate model that approximates the TN decision model. Then the trained surrogate model is equivalently reformulated as mixed−integer linear programming (MILP) constraints and integrated into the vehicle charging optimization framework. Shapley values are further used to analyze the explainability of the tree-based surrogate model. Based on the constraint learning, a data-driven hybrid optimization model is developed for vehicle charging. Case studies validate the approximation accuracy and explainability of the tree-based surrogate model, as well as the effectiveness of the optimal strategy within the PTN.

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, with in the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling, in that long global interconnect lines become signicantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.Most synchronous digital systems consist of cascaded banks of sequential registers with combinatorial logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. The global performance and local timing requirements are satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst case timing constraints. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied and that no race conditions exist.The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network. Interrelationships among these three subsystems of a synchronous digital system are critical to achieving maximum levels of performance and reliability.Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important area of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.The literature in this field exists in a variety of journals and conference proceedings. Examples include the IEEE Transactions of Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE/ACM Design Automation Conference, and a host of related computer, circuits, and CAD conferences. Survey and review articles exist that summarize many of the primary results while providing background and perspective.

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.