Inter-Chip Low-Voltage-Swing Transceivers

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

In this study a new structure was presented to design and simulate a considerably low power and high‐speed 4‐bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal‐oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I ) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 0.36mm2이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

This review paper presents an analysis of the most recent advancements in sub-1V voltage references, addressing the growing demand for ultra-low power consumption and high precision in modern integrated circuits (ICs). Voltage references are critical components in numerous applications, including IoT devices, wearable electronics, and energy-harvesting systems, where power efficiency and accuracy are paramount. It briefly discusses the challenges associated with designing voltage references at such low voltages, such as limited headroom, reduced noise margin, and process variations. Topics include high-order curvature compensation, modified differential pair configurations, and energy-efficient solutions for integrated energy harvesting. These advancements enhance precision and reliability in low-voltage circuits, paving the way for sustainable, low-power electronics and compact devices in the modern digital landscape. It emphasizes the importance of benchmarking different designs against criteria such as power consumption, line regulation, temperature stability, and supply voltage rejection ratio (PSRR). The paper include insights into the state-of-the-art sub-1V voltage reference designs, identification of design trade-offs, and recommendations for future research directions. It underscores the importance of continuous innovation in voltage reference design to address the evolving requirements of ultra-low power electronics. The study here is setting the stage for a detailed analysis of the latest developments in sub-1V voltage references.

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18[Formula: see text][Formula: see text]m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7[Formula: see text]V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47[Formula: see text]nW, at a supply of 0.7[Formula: see text]V. A temperature coefficient (TC) of 42[Formula: see text]ppm/[Formula: see text]C is achieved when the temperature ranges from [Formula: see text]20[Formula: see text]C to 80[Formula: see text]C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

Wireless Sensor Network (WSN) is one of the supporting technologies for the Internet of Things (IoT). However, a large-scale deployment of the WSN faces multifarious challenges. WSN node size and maintenance cost incurred by periodic energy source replacement are among them. From the perspectives of energy sources, these two challenges can be better addressed by Wireless Power Transfer (WPT) technologies in comparison with energy-scavengers or traditional energy-storages. Omnidirectional-Electro-Magnetic (EM)-Radiation WPT-technology appears to be a viable choice. Hence, this work proposes various circuit design techniques in developing the dedicated Power Management Integrated Circuit (PMIC) structures to facilitate implementation of such WPT technology. In detail, this thesis describes (i) a sub-1-V CMOS Voltage Reference (VR) with novel trimming networks, (ii) a Capacitor-Less (OCL) Low Drop-Out Voltage Regulator (LDO) with load-adaptive negative-resistance at the input stage of an Operational Transconductance Amplifier (OTA), and (iii) a compensator-less Square Root Voltage Mode (SRVM) controller for a Pulse Width Modulation (PWM) Discontinuous Current Mode (DCM) Boost DC-DC Converter. To elaborate, the trimming networks aim at minimizing Temperature Coefficient (TC) against process variations and the finite resistance of the CMOS trimming switches in a CMOS Voltage Reference (VR). The loadadaptive negative-resistance helps to boost the DC-gain of the proposed OCL-LDO while improving the current efficiency and ensuring fast-settling and frequency stability. Lastly, the compensator-less SRVM controller is designed to minimize power and area from the discrete compensator circuits in conventional DC-DC converters. Subsequently, structures of three key PMIC building blocks, such as a VR, an OCL-LDO and a boost DC-DC switching converter, are proposed with the aforementioned circuit design techniques. Trimming networks are proposed for a sub-1-volt CMOS VR implemented using the threshold-voltage-difference (Vth) approach. Fabricated in 0.18-m CMOS-technology, the trimmed CMOS VR consumes 0.4 A with a supply voltage of 0.7 V. A TC of 45 ppm/C and a xi Power Supply Rejection (PSR) greater than -55 dB up to 10 MHz. The trimmed VR can also operate under supply voltages from 0.7 V to 1.5 V and operating temperature range from -40 C to 80 C. A fast-settling OCL-LDO enhanced by a load-adaptive negativeresistance is proposed. Such load-adaptive negative-resistance resides at the EA input-stage, which incorporates a Partial-Positive-Feedback (PPF). No compensation capacitors is needed for frequency stability as a result. The overall OCL-LDO is manufactured in 0.18-m CMOS-technology. It achieves a fast settling-time of 2.99 s and 2.05 s against a load step-up and -down respectively between 30 mA and 80 mA in 100 ns. The OCL LDO functions under supply voltages from 0.8 V to 1.5V. It consumes quiescent current of no more than 21 A under no-load condition; it can source as much as 80 mA to the loading ICs.

In this paper a new control algorithm for self-supported Dynamic Voltage Restorer (DVR) is analysed. DVR is used to mitigate the power quality problems in terminal voltage like voltage sag, swell, harmonics etc. Here two PI (Proportional Integrator) controllers are used for regulating the DC bus voltage and the load voltage. The focus of this paper is to reduce the active power injected by DVR. Synchronous Rotating Frame (SRF) theory is used to extract the fundamentals of terminal voltage and reference voltage is genereted. The error between sensed load voltage and reference load voltage is used to generate the control signal for the DVR. The compensation of voltage sag, swell, harmonics is evaluated using the Self-supported DVR. The DVR has been modelled using MATLAB software with its Simulink and Sim-power system (SPS) block set tool boxes.

This brief presents a CMOS voltage reference for ultra-low-power applications, such as in implementable medical devices and energy harvesting-based wireless sensor nodes. In these applications, excellent capabilities to reject interference from power sources and work in low voltage to extend survival periods are critical for the voltage references. A transistor size-ratio determined current generator with high process and voltage independence is implemented by two same-threshold-voltage NMOS transistors, hence obtaining the precise reference voltage with an active load. The proposed circuit is fabricated in a standard 0.18μm CMOS process. Measurement results show that the prototype design provides a 210-mV reference with only 0.027% line sensitivity with a supply voltage from 1.8 V down to 0.4 V. The power supply ripple rejection at 10 Hz, 1 KHz, and 1 MHz is -59, 47, and 53 dB, respectively. The temperature coefficient is 82 ppm/°C in the temperature range from -40°C to +140 °C. Furthermore, the power consumption is only 9.6 nW at room temperature and the active area is 0.021 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/°C, for the temperature range from −55 to 125 °C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of −0.17 % and 822 μV pp , respectively.

0.7-V supply, 21-nW All–MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS

This paper proposes an all MOSFET transistor-based voltage reference with ultra-low power consumption and high PSRR for Internet of Things applications. The reference voltage is computed using the gate source voltages of the five NMOS transistors, excluding the use of any transistors with high threshold voltages. To provide a steady clamping voltage for the current source, a supply voltage stability circuit with a current source is added which enhances the proposed voltage reference line sensitivity and PSRR. It has been designed and simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology to simulate the proposed voltage reference where all MOSFETs function in the subthreshold region with a 0.5[Formula: see text]V minimum supply voltage. The proposed voltage reference produces a reference voltage of 129.7[Formula: see text]mV with a supply voltage range of 0.5–3[Formula: see text]V. Based on simulation results, the proposed voltage reference has an active area of 0.001[Formula: see text]mm2, requires 11.2[Formula: see text]pW of power and has a line sensitivity of 0.021%/V. For a temperature range of [Formula: see text]40∘C to [Formula: see text]C, the circuit achieves a temperature coefficient of 38.2[Formula: see text]ppm/∘C. The power supply rejection ratio of the proposed voltage reference is [Formula: see text]101.5[Formula: see text]dB at 10[Formula: see text]Hz and [Formula: see text]90[Formula: see text]dB at 100[Formula: see text]Hz. The output noise at 100[Formula: see text]Hz and 1[Formula: see text]kHz is 4.68[Formula: see text]and 4.22[Formula: see text][Formula: see text]V/[Formula: see text]Hz, respectively.

There are still some problems in telemetry technique for implantable medical systems now, such as relatively high power consumption, complex circuits or large bulk. In order to solve above problems, an effective pulse position modulation (PPM) method is adopted in this paper, that make possible the design of simultaneously lower power consumption, good communication distance and good displacement tolerance while keeping circuitry simple, particularly in the implantable device. PPM is frequently used in lower power consumption or high reliability systems. We use 2-PPM in this paper, all the coding and decoding processes of PPM are completed with microchip. The approach of transmitting signal is via two magnetic coupling coils, air-cored coil of φ50mm for programmers and ferrite-cored coil of φ3.8mm for implantable device. A magnetic coupled PPM transcutaneous wireless communication resolution is presented in this paper. Full-bridge topology with push-pull driving is adopted as amplifier in programmer. Compared with the common-used class-E amplifier, the full-bridge one is simple and reliable. In this paper, over two inches bidirectional communication distance between implantable device in the body, with titanium container, and programmer outside the body is realized, at the same time, the communication system is with good displacement tolerance and coil displacement mismatch question is well solved. The average power consumption is about 33uA under typical condition for implantable communication device in the PPM system, it is lowered greatly compared with our amplitude shift-keying (ASK) system, ASK’s average power consumption is about 10.3mA at the same test condition.

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW. >

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications.