Interactive two-dimensional design of barrier-controlled MOS transistors

The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this work, a two-dimensional potential distribution formulation/model is presented for double-gate poly-crystalline silicon thin film transistors. The work aims at deriving a potential solution for the threshold voltage estimation of the device under consideration. The Green's function approach is adopted for the two-dimensional potential solution. The developed formulation incorporates the effects due to traps and grain boundaries. The existence of short-channel effects and drain-induced barrier-lowering effects can also be seen from the characteristics. A relation to achieve the targeted threshold voltage with the physical gate dielectric thickness, dielectric constant, substrate doping concentration, grain size and drain–source voltage as parameters is also presented. The model is then extended to evaluate drain current performance. The results obtained show an excellent agreement with numerical modelling based on the finite difference method and also a good agreement with simulation results, thus demonstrating the validity of our model.

The Floating Gate MOS Transistor with Multiple Inputs is a device that offers some advantages with regard to the conventional MOS transistor. However, even today, there is a lack of formal and detailed analysis about the analog model in the literature. An accurate model of this device is very important for designing high performance analog cells. In this document a strategy for modeling the floating gate transistor operating in the weak inversion region based in the adaptation of the EKV model is proposed. The basis for developing a complete theory which allows the modeling of this device model is introduced. This type of modeling can be very useful for high performance analog integrated circuits designers where the transistor concerned here is strongly recommended. Further, this modeling process is also useful for the development of new computational tools for analog circuits simulation.

Intrinsic and generated bulk defects in the gate insulator of silicon insulated gate field effect transistors were examined using a continuous forward-bias pulsed injection technique to inject up to 1017 e/cm2 at 293 and 100 K, for insulator thicknesses ranging between 5.4 and 50.5 nm. The amount of trapping observed at 100 K was about 30 times greater than that at 293 K. The additional trapping at the reduced temperature was determined to come from two sources. One is trapping by existing shallow bulk defects, and the other is an increase in the density of generated bulk defects. The defect generation process is thought to be related to the neutral hole trap becoming unstable during injection, acting as an electron trap. This instability appears to be enhanced as the temperature is reduced to 100 K by a “freeze out’’ effect, or by higher energy carriers that result from a reduction in the thermal scattering. The defect generation rate follows a power law, much like a chemical rate equation, i.e., the rate of defect generation is dependent on the injection current density, much like a chemical reaction is dependent on pressure of the reactive species. The charge centroid of the generated defects, measured from the substrate/oxide interface, was determined at both temperatures and the centroid of the shallow electron traps was determined at 100 K. These were found to be in the range of 6–8 nm at 100 K and 10–16 nm at 293 K. Also, a defect free, or tunneling, region of 2–4 nm extent was determined to exist at each interface. This implies that when the oxide thickness decreases to about 4–8 nm, no threshold voltage shift should result from carrier injection at room, or low temperature, and in fact this behavior was observed in these devices (at least up to 1017 e/cm2 injected). It was found that the shallow traps can be rapidly depopulated by subjecting the devices to ordinary white light during normal device use, pointing to a possible method to improve device reliability at 100 K.

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv ′ is controlled by the voltage differenceV P − Vch, whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value ofV ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P − VS andV P − VD. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI D is derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P − VS, respectivelyV P − VD, through a specific currentI S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

In this paper we consider the use of static analog VLSI circuits for iteratively maximizing cost functions that admit a fixed point recursion. We show through circuit simulation that certain classes of fixed point equations can be solved iteratively via the settling to steady state equilibrium of properly designed static-feedback CMOS circuits biased in the subthreshold region of operation. To demonstrate the power of this approach, we design a family of circuits to compute the right principal singular vector of arbitrarily sized positive real matrices by casting the singular vector extraction problem into a fixed point iterative map. We also illustrate the methodology more simply with a square root solver that uses the Babylonian fixed point equation. All circuits are current-mode translinear circuits with no extrinsic capacitors. This permits fast, low-power computation since the principal delay component is the settling time of the static circuits, and the few transistors required are biased in weak inversion.

The mathematical formulae of six topologies of fractional-order Colpitts oscillator are introduced in this paper. Half of these topologies are based on MOS transistor, and the other half is based on BJT transistor. The design procedure for all of these topologies is proposed and summarized for each one. Stability analysis is very crucial in oscillators’ design, as oscillators should have its poles on the imaginary axis to obtain a sustained oscillation. Hence, determining the factors that control the oscillator’s stability is very important. An intensive study of the stability of Colpitts oscillator is introduced, including different cases for all topologies. Additionally, circuit simulation is conducted using Valsa’s emulator of the fractional-order capacitor for validating the mathematical formulae and the stability criteria. Experimental work is also included to verify the mathematical findings and circuit simulations.

Plasma-induced damage (PID) and bias temperature instability (BTI) are inevitable reliability issues that degrade the performance of transistors. In this study, PID and BTI, depending on the type of antenna layer, are evaluated in current-starved ring oscillators (ROs) to separate degradations in PMOS and NMOS transistors in a 65 nm silicon-on-insulator (SOI) process. Oscillation frequencies of ROs fluctuate with the performance of MOSFET switches between power/ground rails and virtual power/ground nodes. The initial frequencies of ROs with PMOS switches having antennas on upper layers decrease. However, those with NMOS switches become higher than those without PID because high-k dielectrics are damaged by positive charges. The degradation induced by negative BTI (NBTI) in PMOS is 1.5 times larger than that induced by positive BTI (PBTI) in NMOS. However, both NBTI- and PBTI-induced degradations are the same among different antenna layers. The frequency fluctuation caused by PID is converted to threshold voltage shifts by circuit simulations. Threshold voltages shift by 8.4 and 11% owing to PID in PMOS and NMOS transistors, respectively.

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

A 0.25-V calibration-less inverter-based OTA for low-frequency Gm-C applications

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ?, respectively), ? parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.

This paper brings in three transistor models that may be used for weak inversion design: the EKV model, the ACM model and the BSIM3v3 model. The EKV model is used in modeling of weak inversion to offer an accurate prediction of low-voltage, low-current designs. The ACM model gives equations that avoid non-physical interpolating curves between weak inversion and strong inversion region, with the intensions of modeling moderate inversion more precisely. The model is an extension of EKV model and is useful at the limits of weak inversion, where circuit will benefit from drifting into moderate inversion. As a final point the BSIM3v3 model is compared with the EKV model and a good relationship is shown. Although EKV model is considerably less complex as compared to BSIM3v3 model it is sufficiently accurate to model transistors. To demonstrate the ability for circuit analysis a transconductor is used as an example.

In this paper, we present a physics-based small signal model of drain current local variability due to random discrete dopant effect for an n-type epitaxial delta-doped (E $\delta$ DC) MOS transistor. Based on the analogy with flicker noise phenomenon, the concept of inversion charge fluctuation with correlated mobility fluctuation (MF) is utilized. The correlated MF has two components. One is due to Coulomb impurity scattering of the inversion carriers with the ionized impurity atoms. The second component is due to the fluctuation of the effective electric field that results in fluctuation of the inversion charges. The model is verified with calibrated technology computer-aided design simulation results for all bias regions for five different device geometries and three different operative temperatures. Impact of channel engineering for reduction of the drain current local variability is studied in detail.

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack