Interference Cancellation in Broadband Wireless Systems Utilizing Phase-Aligned Injection-Locked Oscillators

Noise factor (NF) is used to quantify the degradation of the signal passing through RF circuits. The spot NF widely used in narrow band low-noise amplifier (LNA) is frequency dependent. It's necessary to redefine the NF for the wideband LNA where the ultra-wideband (UWB) signal pulse is assumed to be of the Gaussian pulse. The average NF suitable for the wideband LNA is discussed firstly. Numerical study on the average NF of LNA for UWB impulse radio is presented in this paper. The average NF is analyzed to quantify the relationship between LNA and Gaussian pulse. A design strategy is suggested that the Gaussian pulse frequency response is optimized to lower average NF. The average NF is equivalent to the spot NF when narrow band assumption is made. For wideband systems with constant frequency response, the average NF is determined by two endpoints frequency summation

A delay- and phase-locked loop (D/PLL) based clock and data recovery (CDR) system enables an independent bandwidth control for jitter transfer and jitter tolerance but requires careful loop design with PVT-sensitive analog building blocks. In this work, an all-digital DLL and a digitally-controlled type-I boosted-gain fractional-N PLL followed by an injection-locked oscillator (ILO) are designed to realize a semidigital CDR system with enhanced frequency tracking capability and low algorithm jitter generation. The proposed CDR designed in 90nm CMOS consumes 26.4mW from a 1.2V supply and occupies the active area of 1.17mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Direct-conversion receiver is the most prevalent receiver architecture today for wireless communications. However, it requires coherent demodulation using the phase-locked loop (PLL)-based carrier recovery techniques, which increases circuit complexity and power consumption of the receiver. This paper presents a novel polar receiver that utilizes two injection-locked oscillators (ILO) stages to extract the modulation envelope and phase components from a received non-constant envelope modulation signal without using carrier recovery circuitry. The implemented prototype can perform π/4 DQPSK and QPSK demodulation with error vector magnitudes (EVM) of 7.5% and 8.2%, respectively, both at 2 Msps and a received power of −40 dBm. Owing to its simplicity, the proposed receiver has great potential as an energy-efficient architecture with low cost for green radio applications.

Injection-locked oscillators (ILO) have widespread use in wireline and wireless systems as fast-locking clock generators, phase noise filters, and frequency multipliers/ dividers, but their modeling and simulation typically resort to SPICE due to their nonlinear, time-varying characteristics. This paper presents a way to simulate ILOs in an event-driven logic simulator such as SystemVerilog, based on a perturbation projection vector (PPV) model. By expressing the continuous-time signals in analytical forms of which coefficients are updated as events, the nonlinear phase response of the ILO can be simulated in an algebraic fashion without numerical integration. The simulation methodology is demonstrated with the modeling examples of a phase-locked loop and a burst-mode clock recovery loop, each employing a injected-locked frequency divider and oscillator, respectively.

The use of phase-locked loops (PLLs) for clock generation in modern microprocessors has been proliferating in recent years. This is because PLLs have the advantages of allowing multiplication of the reference clock frequency and allowing phase alignment between chips. The PLL locks to a reference clock but can generate output clocks that are a multiple of the reference. It is argued that excessive jitter, caused primarily by power supply noise, can detract from the advantages of phase-locked loops. Moreover, in a multichip system, the accumulated phase error must be measured-not just the jitter.

A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

An alternating current (ac)-coupled high-speed receiver analog front end is capable of shifting the input direct current (dc) level without extra current consumption and signal degradation at high frequencies. However, the dc wander due to the high-pass characteristic of the ac-coupled front end may degrade the receiver performance because it equivalently modulates the sampling threshold voltage of the sampler. While this modulation may be negligible for highly dc-balanced input, it shows observable degradation in Peripheral Component Interconnect Express (PCIe) 3.0 receivers operating at 8 Gb/s. In addition, analog equalization is generally required for a PCIe 3.0 receiver front end. This paper presents techniques to add linear equalization and dc wander compensation into an ac-coupled receiver front end. The proposed linear equalization scheme attenuates the low-frequency energy and keeps the high-frequency energy. The proposed dc wander-compensation method is independent of process, voltage, and temperature; therefore, there is no need for calibration or compensation. The proposed schemes have very low power consumption and very good linearity because only passive and linear components are utilized in the main signal path. The proposed schemes were confirmed by simulation.

In this paper, signal interference feedback technique is proposed for an electrically small bandpass filter (BPF) design with low insertion loss. By utilizing signal interference provided by the feedback circuit, transmission zeros can be generated and filter characteristics (center frequency, bandwidth, rejection, stop band) can be controlled by the transmission line parameters. In this work, three transmission zeros are designed to suppress spurious responses, hence wide-stopband as well as high selectivity are achieved. The filter has a simple structure and is constructed using a pair of coupled-line couplers in the main signal path and the feedback, respectively, to provide signal interference. Based on this interference method, a BPF operating at 2.4 GHz is designed and fabricated using an LTCC substrate. The measured results on the fabricated filter show that a wide stopband is achieved with a rejection level of -15 dB up to 4.7f0, roll-off rate of 20 dB/GHz, with an insertion loss of 1.3 dB

This paper presents an inductor-less frequency selective input match wireless receiver front-end utilizing noise cancellation, operational from 0.7 to 3.8 GHz. The main path of the receiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and frequency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm $^2$ . It achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respectively. The chip is supplied by 1.2 V and consumes 22.8–34.9 mA.

This paper analyzes large-scale networks that share the spectrum with interference cancellation (IC). The efficiency of spectrum sharing is determined primarily by interference, which in turn depends on the spatial densities, the interference cancellation method, and the spectrum sharing method, i.e., underlay or overlay. By assuming the Poisson distribution for transmitters, equal transmission power in the same system, and an interference-limited environment, this paper finds the performance gain from IC in terms of spectrum-sharing transmission capacity (S-TC), defined as the number of successful transmissions per unit area while guaranteeing the target outage probabilities of all coexisting systems. The effectiveness of IC is characterized by the coefficient of cancellation (CoC), and specific CoC values are derived for two simple IC scenarios, the strong interferer and the close interferer cancellation, with the assumption of having perfect information for channel states of interfering links and interferer locations. The sum S-TC optimal spatial densities of the two systems are given. Finally, CoC conditions to determine the superiority of an underlay or overlay method are presented. We verify that the underlay method could be preferred depending on the CoCs of coexisting systems; that is starkly different from the case without IC, in which the overlay method is always better.

We present an ultra-low voltage, highly linear, low noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates programmable, in-band feed-forward interferer cancellation at the baseband to obtain high linearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally calibrated interferer cancellation improves the IIP3 and IIP2 by more than 13 dB and 8 dB respectively with very little impact on the receiver noise figure. As such, it breaks the trade-off between linearity and noise figure, making it possible to use a high-gain RF front-end to achieve low noise figure without affecting the linearity of the ultra-low voltage baseband circuits. The 0.6-V 900-MHz direct-conversion receiver prototype integrates a differential LNA, RF transconductors, linear quadrature current driven passive mixers, feed-forward interferer cancellation circuits, baseband variable gain transimpedance amplifiers and second-order channel-select filters. It has a nominal conversion gain of 56.4 dB, noise figure of 5 dB, IIP3 of -9.8 dBm and IIP2 of 21.4 dBm. The receiver operates reliably from 0.55-0.65 V, consumes 26.4 mW and occupies an active area of 1.7 mm2 in a 65-nm low-power CMOS process, of which the feed-forward interferer cancellation circuits consume 11.4 mW and occupies 0.43 mm2 .

This paper presents a novel combination of two fully integrated phase-locked loops (PLLs) to control the oscillation frequency and modulation frequency of a switched injection-locked oscillator (SILO). The SILO is used as an active reflector transponder in a frequency-modulated continuous wave (FMCW) radar system. A fractional-N PLL (RF-PLL) with a tri-state phase-frequency detector (TSPFD) sets the oscillation frequency of the voltage controlled oscillator (VCO) to 2.45 GHz. Another integer-N PLL (modulation PLL) switches the tail current source of the VCO to achieve SILO behavior at the time when the RF-PLL is not controlling the VCO. The RF-PLL supports division ratios from 64 to 511 with a frequency resolution of 0.2 Hz. Reference spur levels are below -48 dBc while the out-of-band phase noise is -103 dBc/Hz at a 1MHz frequency offset. The modulation PLL is based on a Maneatis-cell ring-oscillator supporting modulation frequencies between 6MHz and 20 MHz. Furthermore, the duty cycle of the modulation signal can be set in steps of 0.8 %. Due to the novel TSPFD, the oscillation frequency of the SILO changes only by 36MHz within 10 minutes when the RF-PLL is inactive. The complete circuit is manufactured in a 180nm SiGe BiCMOS process and consumes a total power of 128mW.

A 20–29 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with excellent input return loss (S11), flat and high power gain (S21), and flat and low noise figure (NF) is demonstrated. Wideband input impedance matching was achieved by using the proposed T-match input network to generate two S11 dips. Flat and high S21 was achieved because the inductive-peaking second stage and the current-reused final two stages can compensate the gain degradation of the source-degenerative first stage at medium and high frequencies, respectively. Flat and low NF was achieved by adopting a slightly under-damped Q-factor for the second-order NF frequency response. The LNA consumed 22.07 mW and achieved S11 of −15.5 to −26.8 dB, S21 of 16.2±2.5 dB, minimum NF (NFmin) of 3.1 dB (at 20 GHz), and an average NF of 3.6 dB over the 20–29 GHz band of interest, one of the best reported average NF performances for a 24 GHz band CMOS LNA with bandwidth wider than 6 GHz in the literature.

An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of -95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at -19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of -119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6- μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .