A DLL-based injection-locked frequency synthesizer for WiMedia UWB

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.

This thesis deals with current-mode techniques for ultra-wide band applications. An overview of ultra-wide band (UWB) wireless communications is presented. Two standards for UWB data communications, namely direct-synthesis UWB (DS-UWB) and Multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB are presented. MB-OFDM UWB devices must hop among 14 UWB channels within 9.5 ns, imposing stringent constraints on design of frequency synthesizers. A review of the state-of-the-art frequency synthesizers for MB-OFDM UWB applications is provided. Current-mode phase-locked loops with active inductors and active transformers employed in both loop filters and voltage-controlled oscillators are proposed and their performance in analyzed. Current-mode phase-locked loops decouple the PLL dynamic range from the scaling down of the supply voltage. An active-inductor VCO with both coarse and fine frequency adjustment, a hybrid VCO with a step-down passive transformer loaded with an active inductor, and a hybrid VCO with a step-down passive transformer with a varactor are proposed and their performances are analyzed. These VCOs obtain wide frequency tuning ranges without relying on switched back networks. To meet the timing constraint of UWB frequency synthesizers, Current-mode techniques are further developed for UWB frequency synthesizers. An active inductor with a bank of switched capacitors is proposed to provide fast locking. The bank of switched capacitors eliminates the frequency acquisition locking time of the frequency synthesizer, allowing 9.5 ns phase locking time. The proposed current-mode phase-locked loops, active-inductors oscillators and hybrid oscillators were designed and implemented in TSMC-0.18 μm and IBM-0.13 μm CMOS technologies.

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 p m TSMC process (CM018) to test chip I/O speeds, specijkally, the setup and hold times of I10 registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also employs an eight-stage shift averaging voltagecontrolled delay line (VCDL) to improve the matching between delay stages and thus to equalize the delay of each individual stage. The locking failure or false locking problems are alleviated by using a start-control circuit. setup and hold times are two of the key metrics to evaluate the register or buffer's AC electrical characteristics. Therefore, it is important to test the specifications on setup and hold times. These tests will fail if the delays from the data inputs to the registers and from the clock input to the registers differ such that the data is not valid before (setup time) and after (hold time) the clock is asserted. This may happen due to delays in long buffered interconnect lines and in the clock tree. In order to satisfy the timing requirements, the delay in the clock tree must be larger than the delay for the data input by the setup time requirement, but not so large as to violate the hold time requirement.

A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (VCDL) are used to multiply the input frequency of a clock signal by n. This frequency multiplier is less susceptible to jitter- accumulation as it is a DLL-based design. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 10% to 50% less power than similar clock multiplier circuits. In addition, an architecture for programmable frequency multiplication has been proposed in this paper.

In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-TV phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300-470 MHz and 750-950 MHz RF bands with a 150-kHz frequency step. It provides a phase noise better than -91 dBc/Hz at 150-kHz offset frequency for all the supported channels. The measured settling time is around 350 μS and the reference spurs are lower than -48 dBc. The power consumption of the frequency synthesizer is only 1.7 mW from a 1.2-V supply.

Maintaining satisfactory synchronization between transmitter and receiver is one of the major challenges in carrying out highly efficient ultra-wideband (UWB) communications. For tracking purposes, the delay-locked loop (DLL) concept is applied. The DLL could be considered as a fundamental tracking technique for UWB devices. In this paper, the reference signal is generated at the receiver based on an approach called timing with dirty template. This approach promises to improve tracking performance while reducing receiver structure complexity. After the reference template is generated, we derive first-order and second-order DLL designs for UWB systems. Furthermore, we utilize the benefits of time-hopping codes to enhance noise handling ability of the DLL. Finally, the parameters of the proposed DLL will be selected to optimize tracking behavior in the presence of the ambient noise and Doppler effects. Simulation results show tracking performance across various DLL parameter values.

A low-jitter and fractional-resolution injection-locked clock multiplier (ILCM) with a delay-locked-loop (DLL)-based process-voltage-temperature (PVT)-calibrator is proposed. The ring-type voltage-controlled oscillator (VCO) and the voltage-controlled delay line (VCDL) of the DLL consist of identical delay cells, and they share the same control voltage. Thus, by changing the ratio between the numbers of stages of the VCDL and the VCO, the frequency of the VCO can be calibrated at any target frequencies, noninteger times the reference frequency. As the amount of the unit delay is adjusted continuously by the DLL, the VCO can overcome real-time frequency drifts as well as static process variations; thus, excellent jitter performance can be sustained during any environmental variations. The proposed ILCM, designed in the 65 nm CMOS process, generated output frequencies that range from 1.2 to 2.0 GHz with a frequency resolution of 40 MHz and a 400 MHz reference clock. When injection locked, the integrated jitter from 1 kHz to 40 MHz of the 1.6 GHz signal was 440 fs. The proposed real-time PVT calibrator restricted the degradations of phase noise and jitter over the temperature and the supply variations to less than 0.7 dB and 20%, respectively. The active area was ${0}.{032}\;\text{m}{\text{m}^{2}}$ and the power consumption was 3.6 mW.

This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. The VCO cores cover frequencies from 3.4GHz to 6.8GHz. The programmable output dividers allow generation of the lower frequencies. The frequency resolution of the implemented system is ±20 parts per million (ppm) over -40/85oC. The output power is tunable between -4dBm and +5dBm. The implemented system has a phase adjust feature that allows shifting of the output phase in relation to the reference oscillator ranged from 0° to 180°. It can generate a wide range, high precision, and linear frequency sweep. The sweep rate, frequency step, and frequency range are tunable. The new frequency tuning algorithm, named Yas algorithm, is proposed to improve frequency precision of the synthesizer. To demonstrate the efficiency of the Yas algorithm, the simulation result MATLAB and the experimental measurements are presented. The system consumes 300mA; therefore, it can be powered by Li-Ion battery. The output phase noise is -95.55 dBc/Hz at 1KHz offset from 3GHz. The experimental measurement results demonstrate that the implemented frequency synthesizer can be used for applications, such as oscillator of spectrum analyzer, automatic test equipment, FMCW radars, high-performance clock source for high speed data converter

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

The industry is merging two different wireless personal area networks (WPAN) technologies: Bluetooth (BT) and WiMedia ultra wide band (UWB), into a single BT over UWB (BToUWB) specification. The goal is to provide low cost, low power and a wide range of data rate wireless communications for multimedia and mobile applications. The complexity to study such a system requires the development of a virtual prototype at a high- level of abstraction. The model needs a fast simulation time in order to explore the algorithms necessary for the merging of the standards. Moreover, as the merging is still in a standardization phase, this virtual prototype helps to actively participate to this effort. The aim of this paper is to provide an overview of the methodology used to create a virtual prototype of a BToUWB device.

A new closed-loop autocorrelation system is proposed in the paper. It is based on a conventional autocorrelator; however, the fixed delay is replaced by a variable delay line and the autocorrelator output is fed back to control the delay. The variable delay can be realised by a SAW voltage-controlled variable delay line (VCDL). Adetailed analysis of the loop is given. It is shown that for some special inputs, the loop performs as a frequency-measuring system, as an instantaneous frequency measurement (IFM) or as a wideband linear FM discriminator. It is further shown that, in the presence of noise, the loop behaves similarly to a frequency modulation feedback (FMFB) loop. Therefore, the output SNR can be improved (in comparison with conventional FM discriminators) by appropriately choosing the loop parameters. Experimental results of a system implemented using an SAW VCDL are presented and are shown to support the analysis.

The phase noise spectrum of a single loop frequency synthesizer for S-band, which can be utilized in broadcasting terminals, was predicted based on the analyses for phase noise contributions of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of a frequency synthesizer. To accurately model the phase noise contributions of noise sources in the frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for the reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of the phase-locked loop. The frequency synthesizers were fabricated and the phase noise prediction model was evaluated by measured data and prediction data.

A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the lock state, which is achieved by decreasing the charge-pump (CP) current during the idle interval of the phase detector. The proposed DLL frequency synthesizer, which has been realized in a CMOS 90-nm technology, consumes 20 mW at 1.2 V supply with the frequency-multiplied output covering from 0.45 to 5.4 GHz. For 850-MHz input clock, the phase noise at 1-MHz frequency offset after ×6, ×3, and ×2 is -121.4, -127.4, and -129.7 dBc/Hz, respectively. The corresponding output spurs achieve -26.2, -36.8, and -39.2 dBc for ×6, ×3, and ×2, which are 7.6, 5.9, and 15.4 dB lower than those using a conventional current-steering CP, respectively.

본 논문에서는 전압제어지연단(Voltage Controlled Delay Line : VCDL)을 이용하여 기존의 위상고정루프와 다른 형태의 위상 지연고정루프(Phase Delay Locked Loop)를 제안하였다. 이 구조를 이용하여 기존의 위상고정루프의 2차 또는 3차 루프필터(Loop Filter)를 단하나의 커패시터로 구현하여 칩의 크기를 크게 줄였다. 새로이 제안하는 듀얼루프 위상 자연고정루프에서는 전압제어지연단 경로의 커패시터와 전하펌프의 전류 크기를 조절함으로서 작은 이득 값을 가지는 전압제어지연단을 사용할 수 있다. 제안된 회로는 <TEX>$0.18{\mu}m$</TEX> CMOS 공정의 파라미터를 이용하여 Hspice로 시뮬레이션을 수행하고 회로의 동작을 검증하였다. In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V <TEX>$0.18{\mu}m$</TEX> CMOS process and proved by Hspice simulation.