이중루프 위상.지연고정루프 설계

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty.

A Flash analog-to-digital converter (ADC) architecture operating in time-domain is presented. The proposed ADC uses voltage controlled delay lines (VCDLs) and time-domain comparators instead of pre-amplifiers and voltage-domain comparators in the conventional Flash ADC. Due to the time-domain operation, the proposed Flash ADC benefits from fast switching speed of advanced CMOS process. A key property of the proposed ADC is that its linearity is not affected by the non-linearity of the VCDL, due to the identical VCDLs that are used in both the input signal and reference voltages.

A low-jitter and fractional-resolution injection-locked clock multiplier (ILCM) with a delay-locked-loop (DLL)-based process-voltage-temperature (PVT)-calibrator is proposed. The ring-type voltage-controlled oscillator (VCO) and the voltage-controlled delay line (VCDL) of the DLL consist of identical delay cells, and they share the same control voltage. Thus, by changing the ratio between the numbers of stages of the VCDL and the VCO, the frequency of the VCO can be calibrated at any target frequencies, noninteger times the reference frequency. As the amount of the unit delay is adjusted continuously by the DLL, the VCO can overcome real-time frequency drifts as well as static process variations; thus, excellent jitter performance can be sustained during any environmental variations. The proposed ILCM, designed in the 65 nm CMOS process, generated output frequencies that range from 1.2 to 2.0 GHz with a frequency resolution of 40 MHz and a 400 MHz reference clock. When injection locked, the integrated jitter from 1 kHz to 40 MHz of the 1.6 GHz signal was 440 fs. The proposed real-time PVT calibrator restricted the degradations of phase noise and jitter over the temperature and the supply variations to less than 0.7 dB and 20%, respectively. The active area was ${0}.{032}\;\text{m}{\text{m}^{2}}$ and the power consumption was 3.6 mW.

A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (VCDL) are used to multiply the input frequency of a clock signal by n. This frequency multiplier is less susceptible to jitter- accumulation as it is a DLL-based design. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 10% to 50% less power than similar clock multiplier circuits. In addition, an architecture for programmable frequency multiplication has been proposed in this paper.

A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm2 and consumes 15.56 mA.

This paper presents the design and simulation results for a Federal Communication Committee (FCC) complaint current starved delay line based Ultra Wide Band (UWB) Gaussian pulse transmitter, which is designed for operating in the 3.1–10.6 GHz range. The wavelet is a mono cycle Gaussian impulse wave, which is practically well suited for low cost, low power, low data rate wireless data transfer such as in wireless body area network (WBAN) applications. The transmitter operating frequency and bandwidth (BW) is controlled using a dc voltage provided at the input stage of a voltage controlled delay line (VCDL) and this aspect can be exploited for increasing the communication coverage area without compromising on the power consumption. A Gaussian wave shaping is performed for FCC compliance and the simulation has been carried out with 130 nm technology. The simulation of our design suggests an average dynamic power consumption of 1.11 mw for an energy efficiency of 14.2 pJ/pulse. The proposed IR-UWB transmitter design though a bit inferior in terms of the power efficiency, can claim superior performance with respect to tuning the BW, which is very relevant in a cognitive wireless networking scenario with other interfering signals.

In this paper, a frequency doubler is designed that converts from 1.15 GHz input signal to 2.3 GHz output signal using TSMC 0.18 CMOS technology. The proposed doubler consist of a fully adjustable Schmitt trigger (FAST), time-delay components, XOR gate and a voltage controlled delay line (VCDL). Time-delay components use RC integrator and comparator. Advantages of this topology include good fundamental frequency and harmonic frequency suppression, compact layout and low power consumption. The desired signal at 2.3 GHz is 0.871 dBm. The fundamental frequency at 1.15 GHz and third harmonic frequency at 3.45 GHz approximately 37 dBc below the 2.3 GHz signal. The fourth harmonic frequency at 4.6 GHz is approximately 24 dBc below the 2.3 GHz signal. The power consumption is 11.07 mW and the phase noise of the output signal is 100.5 dBc/Hz at 10 KHz offset.

This paper presents a new skew control technique for a high speed mobile display serial interface. Unstable frequency and distorted duty ratio of recovered clock from the skew of data and strobe can be adjusted simultaneously by the proposed adaptive strobe delay controller (ASDC). Clock regulation is important because a raster image is re-constructed by using pixel clock from serialized host sending image data. By converting detected skews to voltage level and using a voltage controlled delay line (VCDL), the proposed adaptive skew control technique solves the problems of image distortion which are caused by several mismatched skew elements between data and exclusive OR (XOR) encoded strobe signal. The proposed skew controller and its related transceiver were implemented and also verified using a mega-pixel mobile image sensor. This technique has an output duty error of less than 3% under the instantaneous duty error of 20% and the implemented systems shows a good image quality from 500 MHz to 1 GHz normal operation with 3.5 mW power dissipation.

We propose in this paper a new architecture of a CMOS integrated pulse width modulator (PWM) used to control the duty-cycle of square waveforms. The architecture of the proposed PWM is based mainly on an improved voltage controlled-delay line (VCDL) which requires a very small integrated area. The first version of this PWM allows duty-cycle control range of 0% to 50%, and the second version with duty-cycle control this range from 0% to 100%. The two versions of the proposed PWM are dedicated for the control of the power level of switching power amplifiers and are suitable for integrated DC-DC voltage conversion applications. Hspice simulation results show that the proposed PWM is able to achieve a large duty-cycle control range with high resolution.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.

This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with a direct implementation in CMOS technology, which makes possible to construct also the UWB pulse generator. Simulations show that the signal obtained as pulse sequences that are delayed using phase modulation can be used to drive an UWB generator that outputs pulses satisfying the requirements regarding the regulated output spectrum.

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 p m TSMC process (CM018) to test chip I/O speeds, specijkally, the setup and hold times of I10 registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also employs an eight-stage shift averaging voltagecontrolled delay line (VCDL) to improve the matching between delay stages and thus to equalize the delay of each individual stage. The locking failure or false locking problems are alleviated by using a start-control circuit. setup and hold times are two of the key metrics to evaluate the register or buffer's AC electrical characteristics. Therefore, it is important to test the specifications on setup and hold times. These tests will fail if the delays from the data inputs to the registers and from the clock input to the registers differ such that the data is not valid before (setup time) and after (hold time) the clock is asserted. This may happen due to delays in long buffered interconnect lines and in the clock tree. In order to satisfy the timing requirements, the delay in the clock tree must be larger than the delay for the data input by the setup time requirement, but not so large as to violate the hold time requirement.