Introduction to the testing of integrated circuits

The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded on-chip in modern ICs to handle and monitor various activities. Many defects are handled at IC manufacturing; however, there are many problems occurring after ICs are being mounted on PCBs. In many cases, it is unfortunately not possible to reproduce the problem when the electronic system is taken to a repair shop. These problems are known as No Trouble Found (NTF). One obstacle is the limited access to the on-chip DfT instruments that exist in most ICs. We will discuss access to on-chip DfT instruments through the life-time of electronic systems. We will focus on electronic systems using the IEEE 1687 standard.

<div class="htmlview paragraph">As the United States Air Force (USAF) in addition to the rest of DoD and American society become increasingly dependent on smaller, faster, cheaper, higher-performing integrated circuits (IC), digital, technologies that have more functionality, we must not overlook the fact that better-performance does not come without its price. In this paper, we discuss the integrated circuit; solid-state and IC history; IC functionality; IC manufacturing process; and silicon and silicon dioxide heat transfer rates. We discuss customized ICs such as Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Micro-Electro-Mechanical Systems (MEMS). We discuss the Fourier heat equation. We discuss how increasing the numbers of transistors and their support components increases the density relating to the interior of such semiconductor materials. We discuss the purposes of reducing size and weight of an overall system; that the reduction of IC exterior dimension along with an ever increasing need to increase the interior numbers of components and their support mechanisms for performing ever more functions increases internal heat. We discuss how this trend could lead to the generation of higher internal IC temperatures as well as indeterminate states of IC functionalities. We discuss traditional and non-traditional solutions for removing IC heat.</div>

With the rapid development of advanced technologies in the Internet of Things era, higher requirements are needed for next‐generation electronic devices. Fortunately, organic thin film transistors (OTFTs) provide an effective solution for electronic skin and flexible wearable devices due to their intrinsic features of mechanical flexibility, lightweight, simple fabrication process, and good biocompatibility. So far considerable efforts have been devoted to this research field. This article reviews recent advances in various promising and state‐of‐the‐art OTFTs as well as related integrated circuits with the main focuses on: (I) material categories of high‐mobility organic semiconductors for both individual transistors and integrated circuits; (II) effective device architectures and processing techniques for large‐area fabrication; (III) important performance metrics of organic integrated circuits and realization of digital and analog devices for future smart life; (IV) applicable analytical models and design flow to accelerate the circuit design. In addition, the emerging challenges of OTFT‐based integrated circuits, such as transistor uniformity and stability are also discussed, and the possible methods to solve these problems at both transistor and circuit levels are summarized.

The electronics Integrated Circuit (IC) chips have enabled us to create intelligence on silicon (Si). Hence the impact of electronics manufacturing cuts across the entire industrial ecosystem. The IC chip is arguably one of the most profound inventions of the last century. Since the invention of the semiconductor transistor towards the end of the year 1947, the entire electronic industry was struggling to deal with the tyranny of numbers — the difficult problem of manually assembling a large of number of transistors on a board to realize complex circuits. This is when Jack S. Kilby entered the stage in the year 1958. He was a hands-on engineer with a lot of imagination and intuition, but grounded to reality with a lot of practical experience. He proposed a revolutionary concept of creating all components of an electronic circuit, insitu, on a single semiconductor piece. He successfully implemented this idea on September 12, 1958, by realizing a phase shift oscillator on a small piece of germanium (Ge), the first ever electronics IC chip. The importance of this milestone in the modern history of science and technology is highlighted by the fact that Jack Kilby received the Nobel prize in Physics, in the year 2000. The story of Jack Kilby and his remarkable achievements are very inspiring for all ages.

Due to the fact that the traditional Digital Electronic Technology (hereinafter referred to as DET) experiments bear sufficient reference material, elaborate design plan and complete design circuits (which makes it difficult for the students to design some experiments by themselves innovatively), but fail to bear enough experimenting methods, combined with the requirements raised by the competitions for experiment case teaching of elementary curriculums on electronic engineering and technique, in order to make some changes to the traditional experiment teaching, the paper innovated a new experiment case for the design of Rock-paper-scissors Game. In the design, two methods, Digital-integrated-circuit method and programmable-techniques method, are adopted to make it come true. When adopting digital-integrated-circuit method, right integrated circuit components will be employed according to the game-designing plan, using the software of Proteus to simulate it first, followed by debugging and testing of the hardware circuits on the bread board. The programmable-techniques method can describe the functions of the game on the development platform of the software of Quartus II by programming, adopting HDL (hardware description language). After right simulation, the programs will be downloaded onto FPGA experimental boxes or development board to realize the design of the game. The experimental case of Rock-paper-scissors Simulation Game is interesting and novel, which tends to stimulate the students to explore new world, study and innovate new things on their own. The adoption of the two methods will not only further enhance students’ knowledge application ability and engineer practice ability, but also help them better understand the difference of an experiment between the traditional and modern method, which will, in turn, understand the significance and value of programmable techniques in digital system designing.

Advances in chip technology have made modern life possible, and without semiconductor chips, devices such as smartphones, TVs, and computers would not work. The design and manufacture of the chip determine the function and application range of the device. Through continuous innovation and improvement of chip design and manufacturing technology, more functions, higher efficiency, and smaller size devices can be achieved. In these fields, the application of chips and integrated circuits not only improves the performance and function of equipment but also promotes the development of digital society and the application of intelligent technology. This paper explores the critical role of chip technology in various engineering domains, focusing on the advancements in integrated circuits (ICs) and semiconductor materials. It discusses the challenges and developments in chip performance, including response and working speeds, the evolution of RF devices, and the integration of artificial intelligence in chip programming. Artificial intelligence and machine learning technologies are revolutionizing the approach to chip design.

As a core component in electronic circuits, the size of inductors is crucial for the thin-film integration and miniaturization of circuits. Although various miniaturized inductors have been fabricated by using integrated circuit technology, their low current-carrying capacity and small inductance values cannot meet current application requirements. Therefore, this paper designs an inductor chip based on a double-layer parallel (DLP) array microcoil structure. Experimental verification demonstrates that the developed DLP inductor exhibits a far superior rated energy storage capability per unit area compared to other single-layer inductors, along with excellent thermal performance. Meanwhile, the 4 × 3 DLP array can withstand a maximum DC current of 4.25 A. This structural innovation provides a meaningful thermal–electromagnetic co-design reference solution for highly reliable integrated power modules.

Semiconductor materials exemplify humanity's unwavering pursuit of enhanced performance, efficiency, and functionality in electronic devices. From its early iterations to the advanced variants of today, this field has undergone an extraordinary evolution. As the reliability requirements of integrated circuits continue to increase, the industry is placing greater emphasis on the crystal qualities. Consequently, conducting a range of characterization tests on the crystals has become necessary. This paper will examine the correlation between crystal quality, device performance, and production yield, emphasizing the significance of crystal characterization tests and the important role of high-precision synchrotron radiation X-ray topography characterization in semiconductor analysis. Finally, we will cover the specific applications of synchrotron radiation characterization in the development of semiconductor materials.

Advances in interconnect technologies, such as the increase of the number of metal layers and 3-D stacking technique, have paved the way for higher functionality and superior performance while reducing size, power, and cost in today's integrated circuits and package products. With the increase of clock frequency and edge rates as well as the continuously downscaling of feature size and 3-D interconnect technologies in high-speed systems, signal integrity (SI) effects such as signal delay, reflection, attenuation, dispersion and crosstalk have become one of the dominant factors in current deep sub-micrometer CMOS technologies limiting overall performance of high-speed systems.Another major difficulty is the power integrity (PI) issue. For example, IR drop is caused by the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. Chip designs are susceptible to IR drop, especially when the integrated circuit (IC) supply voltage Vdd decreases with the scaling of silicon processes. IR drop is proportional to the resistance of the power/ground plane. When the resistance of power/ground plane increases, with the shrinking of complex geometries, the IR drops will in turn increase as well. To further confound the difficult issue, the rise of the thermal temperature due to the current carrying interconnects also has tremendous impact on the IC performance and reliability. Current flow in a VLSI interconnect can cause a power dissipation, which is referred to as Joule heating or self-heating. The Joule heating effects are becoming increasingly significant with the shrinking scale of silicon process because of the increase of on-chip power density, inclusion of more metal layers with higher densities, and the use of dielectric materials with lower thermal conductivities. Subsequently, the temperature effects on the electrical performance of 3D systems should be carefully considered as well in the electrical designs.Unfortunately, almost all practical SI and PI problems are multi-physics in nature, and various physical phenomena are usually interacting and coupling to each other. For instance, the resistivity of most conducting metals increases linearly with the increases of the surrounding temperature resulting from the Joule heating by electric currents flowing through the conductors. Therefore, in order to accurately characterize the performance of high power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electric and thermal effects and the intimate couplings between them.In this paper, we propose to use non-conformal, non-overlapping domain decomposition methods (DDMs) for the signal integrity analyses and thermal-aware DC IR drop co-analysis of high-power IC-Package-PCBs. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a result, the troublesome mesh generation task for complex ICs can be greatly subdued. Moreover, the proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDMs for both conduction and steady state heat transfer analyses with a two-way coupling between them. Furthermore, we extend the non-conformal DDM to study transient thermal temperature distribution within complex ICs. Numerical examples, including an IC package and an IC-Package-PCB, demonstrate the flexibility and potentials of the proposed non-conformal DDMs for SI analyses and thermal-aware DC IR-drop co-analysis.

Metal oxide (MOX) gas sensors are widely used in electronic noses because of the small size, long life time and low cost. To improve compactness and lower the cost of electronic noses, simple and integrable interface circuits should be designed. The main problem to deal with is the wide range of sensor values to acquire. The proposed interface adopts a circuit architecture which avoids the use of multiple ranges (i.e., scaling factors), but still provides wide input range capability and short measuring time. A single-supply solution has been implemented to facilitate the integration in a single chip together with the digital electronics for data processing. In particular, the fabrication of the front-end in an integrated circuit by using standard CMOS technology has been successfully evaluated. Experimental results conducted by means of simulations as well as real tests with a discrete-component prototype board have demonstrated the effectiveness of the proposed approach.KeywordsElectronic NoseDigital ElectronicShort Measuring TimeOperational Transconductance AmplifierThreshold Voltage VersusThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Chapter 9 - Electrical

Efficiency and accuracy are the two main factors to develop the competence for the integrated-circuit (IC) packaging industry. An IC packaging house needs to deal with problems integrating production flows of wafer in, packaging, test, and shipping in order to provide clients instant and accurate products and services information. Radio frequency identification (RFID) technology is an effective electronic information carrying device to collect and alter data. In this study, RFID technology, combined with RosettaNet network and enterprise resource planning (ERP) system, is applied to resolve the wafer receiving and inventory transaction problems. An electronic material flow control system for IC packaging houses is developed using Oracle application implementation methodology to integrate RFID technology, RosettaNet network, and ERP system. The developed electronic material flow control system is implemented in a local IC packaging company. Results from this study suggest that labor cost and man-made errors are reduced due to the significant improvement for wafer receiving process and inventory transaction process using RFID technology. Besides that, the developed material flow control system enhances the capability of the ERP systems so as to greatly reduce operators' workload and operation costs for IC packaging houses.

Advances in device technology are progressing at such a rate that the functionality of integrated circuits (ICs) nearly doubles every year. The evolution of device technology has yielded devices with clock rates in the GHz range and rise and fall times in the order of a few pico seconds. Without a proper design, ICs often generate high radiated and conducted emissions. The customer can no longer assume that the system in which modern ICs are implemented will meet the regulatory limits and performance compatibility with other electronic devices. This paper deals with the characterization of the electromagnetic emission of ICs, especially the so-called 1 /spl Omega//150 /spl Omega/ method (IEC 61967-4) will be used to measure the conducted emission of an EMC test chip. In particular, the problem of this method when applied to measure the emission of a slew rate controlled output driver is discussed. Higher emission results caused by the 150 /spl Omega/ coupling network (which is not present in conventional applications) have been experimentally evaluated by simulations and measurements.

With the development of integrated circuit (IC) chips, many elongated chips with small amounts of textures have begun to be used in IC packaging and manufacturing. Traditional template-matching methods are not effective for positioning these chips; this limitation results in IC equipment that cannot accurately pick up an elongated IC chip or may package a nonworking IC chip onto an electronic device. In this paper, a novel region-based normalized cross correlation algorithm that uses a signal function to separate the influences of the IC chip and the background pixel information is proposed. To obtain an increased speed, the bounding box of the IC chip is employed to rapidly estimate the region of interest of an IC chip in a target image. Various experiments using LED sorting equipment demonstrate that our algorithm results in correct positioning for elongated IC chips and can distinguish good chips from nonworking chips with reasonable accuracy. When the size of the target image is 512 × 512 pixels and the size of the template image is smaller than 140 × 140 pixels, the matching time of our algorithm is less than 14 ms. This algorithm may have many applications in the field of IC packaging.

Integrated Circuits (ICs) are the cardinal elements of modern electrical, electronic and electro-mechanical systems. Amid global outsourcing of ICs' design and fabrication and their growing applications in smart manufacturing or Industrie 4.0, various hardware security threats and issues of trust have also emerged. IC piracy, counterfeiting, and hardware Trojans (HTs) are some of the key hardware threats that merit the attention of manufacturing community. It is worth noting that the lower abstraction levels (ICs) are falsely assumed to operate securely. The proposition, therefore, is that if an operating system (higher abstraction level) is considered to be secure while operating on a compromised IC (lower abstraction level), would it be prudent to regard this implementation as secure? The purpose of this paper is to highlight IC level threats with an emphasis on hardware Trojans that pose a significant threat to smart manufacturing environment in the wake of Industrial Internet of Things (IIoT).