Investigation on PCB related failures in high-density electronic assemblies

The article also investigates the min. solder volume request for solving Gold embrittlement issue in the limited condition. Gold (Au) embrittlement was known and had been studied for a long time. It will reduce the solder joint toughness not just only in reliability test but in manufacturing process. This kind of failure even occurs just after SMT process, it means we could not apply glue to protect the component from drop-off. The concentration of Gold is the major concern of this failure mode. How to dilute the concentration of Gold from substrate design, component manufacturing, soldering material selection and substrate manufacturing is final goal of forming a robust solder joint. The component drop-off was found in the latter process of SMT. The investigation started from failure mode definition. CSA (Cross Section Analysis) and EDS (Energy Dispersive Spectroscopy) were performed to observe the solder joint structure and alloy composition. Abnormal high concentration of Gold element reveals the Gold embrittlement is the major root cause of solder joint crack. Reducing Gold concentration started from the source of Gold surveying. Soldering related material investigation result shows no abnormality in substrate pad and solder paste but high risk in the soldering terminals of the component. The thicker Gold plating of the component is the major source of high Gold concentration in the solder joint. In general substrate manufacturing process such as desktop motherboard, it might not occur due to the sufficient solder volume provided by enough space and thicker stencil could cover the issue. In this case, the Gold plating thickness is unchangeable, so we only focus on substrate surface treatment and fine tune SMT process parameters to dilute the Gold concentration. The improvement DoEs were conducted for different substrate surface treatment, solder volume and reflow profile with different component batch. For substrate surface treatment, we changed it from ENIG (Electroless Nickel/Immersion Gold) to ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold) for better solder joint strength. To increase solder volume, we enlarge the stencil aperture. For reflow profile fine tune, higher and lower peak with longer soaking time were verified for Gold diffusion. CSA and shear test were performed to confirm the solder joint and compare the joint strength. From the DoE results known, the positive factors solder joint strength enhancements are surface treatment and solder volume. ENEPIG solder joint interface is stronger than ENIG solder joint, but it can't dilute the Gold concentration directly. Solder volume increasing is most obvious factor to dilute the Gold concentration. Therefore, in SiP (System in Package) module production, tiny solder joint and high component density restrict the stencil design. The article also investigates the min. solder volume request for solving Gold embrittlement issue in the limited condition.

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.

The purpose of this paper is to study the temperature effect on the Print Circuit Board (PCB) and the solder joints in the vehicle under working condition of the engine. Thermal-stress test has been used to evaluate the reliability or fatigue life of the PCB using commercially available Finite Element Analysis software, ANSYS. The thermal deformation distribution of the PCB and stress of the solder joints can be obtained. The modal analysis was carried out under the thermal and normal condition. The frequency, mode shapes, deformation and stress were obtained. It is observed that the frequency of the overall PCB assembly was decreased under thermal condition as compared to that under normal condition. The position of maximum temperature was located around the top edge of solder joints, which was close to package. And the position of maximum deformation and stress was also located around the top edge of the solder joints, which was close to package. This paper obtains the thermal stress and thermal deformation of the PCB and solder joints in the vehicle and compare the frequency of the PCB assembly under the thermal and normal condition.

Printed circuit boards (PCB)and SMD packages are made from different materials which coefficients of thermal expansion can differ much. Hence, under thermal load, e.g. board assembly or at field conditions, PCB and package deformation and deviation from the initial state often occur as warpage. During board assembly this warpage can cause failures such as open solder joints and/or shorts of solder joints. In this paper, the use the of shadow moire technique will be introduced for capturing the warpage under thermal loads. Measurement results of single substrates and a selected BGA package will be shown. Furthermore, a design process for PCBs to be applied for investigation of the influence of assembly process parameter will be described. It is assumed that the applied variations and their influence on the assembly quality are linked by the equilibrium of mechanical forces between PCB, BGA and solder joint. Additionally, it is assumed that mechanical stress - especially in out-of-plane direction-may occur in the solder joints. These thoughts apply for soldering process as well as temperature cycling conditions. A finite element model was implemented to analyze the stress for the selected BGA under defined conditions and to investigate warpage impacts on reliability. Finally, a novel approach to measure the electrical functionality will be introduced addressing BGAs under test which come with a high number of connections.

The conversion to lead-free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity of pad cratering in Printed Circuit Boards (PCBs) [1, 2]. In general, lead-free solder joints are stiffer than tin-lead solder joints, and some lead-free compatible PCB dielectric materials are more brittle than conventional tin-lead compatible PCB materials. These two factors, coupled with the higher peak reflow temperatures for lead-free assembly, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath the BGA corner pads. The likelihood of pad cratering occurring in any given assembly depends on several factors including, but not limited to the BGA package size, construction and surface finish; and the PCB pad size, material and surface finish. Standard assembly level bend and shock tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures. However, with these standard assembly level tests, it is difficult to determine if the failures occur due to a weaker PCB structure or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes. In this study, an easy-to-implement test method is presented in detail, along with calibration and test results comparing a broad spectrum of PCB attributes. Different dielectric materials and pad sizes were evaluated to develop a comparative metric that can be used to rank-order different material/pad size combinations. The results were generated over different pull temperatures and multiple reflows, to study the effect of temperature on dielectric mechanical strength characteristics. Ultimately, these metrics can be used to optimize PCB design, thus mitigating pad cratering potential.

In-process failures were experienced during printed circuit board (PCB) SMT assembly of a 16 Quad Flat No Leads (QFN) device. The failures appeared to be solderability related with QFN unit I/O pads not soldering robustly and sometimes leading to QFN detachment following board mounting. When assembly did take place on affected QFN units, the resulting solder joint was observed to be weak. This paper reports on very systematic analyses of the QFN device I/O pads using optical inspections, AES surface, AES depth profiling, SEM/EDX, SIMS, FIB and TEM cross-sectional measurements to determine the root cause of the failure and the failure mechanism. The detached QFN units, suspect and good unsoldered units, passing and failing units obtained from customers were examined. The industry standard surface mount solderability testing was performed on good and suspect parts, and all were observed to pass as evidenced by >95% coverage of the I/O pads. Optical inspections and a wide variety of physical analysis of the pads on fresh parts showed no anomalies with only the expected Au over Pd over Ni found. AES analysis was performed including depth profiling to look for any issues in the NiPdAu over base Cu plating layers that could be contributing the solderability failures. The AES depth profiling indicated AuPd film on the Ni under layer for the I/O pads as expected. No unexpected elements or oxide layers were observed at any layer. Then, one failing and one passing units were compared by doing FIB cross-section, FIB planar section and TEM cross-section analysis. The cross-sectional analysis showed rough Ni surface for the failing units, while the Ni surface was relatively smooth for the passing unit. Further, finer Cu grains and Ni grains were observed on the passing units. Additionally, the lead frame fabrication process mapping showed rough Cu, Ni “texturing” and use of low electro chemical polishing (ECP) current on the bad units compared to that of the good units. All affected bad units were confirmed coming from a second source Cu supplier with the rough Cu. The weak and irregular NiSn IMC formation on the bad units caused IMC separation and possible spalling during board solder reflow primarily due to the rough base Cu and irregular grain sizes and resulting lower ECP lead frame plating current. A possible final factor was marginally low Pd thickness. In conclusion, the 16 QFN device solderability failure root cause summary and the lessons learned from a wide variety of analysis techniques will be discussed.

PurposeThe purpose of this paper is to examine out‐of‐stock (OOS) challenges in the independent grocery sector with a special emphasis on in‐store root causes. The analysis aims to assess the extent and root causes for OOS in the independently controlled retail sector and provide a comparison of these results with the centrally controlled chain sector in Denmark. The paper also seeks to examine the practices and challenges of store ordering and store replenishment processes in the independent sector and identify practical implications for store management and other members of the grocery channels.Design/methodology/approachThe research design includes two studies. Study‐I surveys and compares the extent and root causes of OOS of 42 stores from eight chains in the two sectors. Study‐II identifies, based on qualitative interviews with 17 store managers/owners of independent stores, specific insights on store operations.FindingsThe quantitative study shows that the OOS rates in the independent sector are significantly higher than in the centrally organized sector. Furthermore, the independent grocery sector faces OOS challenges in more categories than the centrally controlled sector. The study also reveals a very large variation in the performance of independent stores. Contrary to the centrally controlled chain store sector, the major root cause for OOS in the independent sector is found in the store ordering process. The qualitative study shows that the main discriminating issues between stores with a low and a high OOS rate are: store management emphasis and commitment to OOS issues; the resulting priority and managerial guidance in store ordering and store replenishment tasks; the stability of staff and the proper planning for replenishment peaks; the store size and resulting space conditions; and the use of appropriate decision heuristics and use of inventory in store ordering.Practical implicationsThe findings have practical implications for store management as it reveals practices to pursue and to avoid. Also, it is argued that the findings have implications for the other members of the grocery channels.Originality/valueEmpirically, this paper explores two issues not being dealt with in depth in previous research, i.e. the OOS challenge in the independent sector and the emphasis on store operations.

Plated through holes provide conductive connection among different copper layers, and mechanical support for components. Plated through hole process includes many steps such as drill, desmear, micro-etch and electroless copper plating. Improper control of any step will lead to plated through hole defects. In the present study, an open circuit failure caused by one of plated through hole defects, inner-layer separation, was found. The inner-layer separation existed in all of four copper layers. The root cause of the inner-layer separation defect was found and the defect could be duplicated. Corrective action was implemented.

Electroless nickel (Ni)/immersion gold (Au), an alternative metal finish on printed circuit board (PCB), has been used successfully for many electronic products. However, brittle fracture of PBGA packages soldered on this metal finish was reported recently by several companies. This paper describes brittle fracture in mechanical testing of thermal enhanced, cavity-down PBGA packages, in the as-reflowed and the aged conditions. In the as-reflowed condition, the fracture is a cleavage between PBGA solder balls and PCB conducting pads. The fracture loads, determined from four-point bending, were typically half of that for peeling off PCB conducting pads. Failure analysis showed that the fracture occurred at the interface between Ni/sub 3/Sn/sub 4/ and Ni-P. Three possible failure mechanisms were explored: (1) phosphorous segregation at the interface, (2) contamination or oxidation during the Ni-Au plating or after plating via diffusion, and (3) brittle fracture of Ni-P and Ni/sub 3/Sn/sub 4/. After aging at 150/spl deg/C for a few days, the AuSn/sub 4/ particles, once in the interior of solder joint in the as-reflowed condition, migrated onto the interface. The weak adhesion between Ni/sub 3/Sn/sub 4/ and AuSn/sub 4/ resulted in a more brittle fracture than that before the aging. This Au-related brittle fracture occurred although the Au concentration in solder joint was only 0.1 wt%, much less than 3 wt%, the rule of thumb concentration for brittle solder joint. The Au-related interfacial fracture may be eliminated by reflow after the aging which moved the AuSn/sub 4/ back to the solder joint interior.

As a fundamental study of the high frequency printed circuit or wire-bonding, the transmission characteristics and magnetic near field intensity distribution for the modeled printed circuit board (PCB), which have the soldered thin wire line are investigated experimentally. The size of a modeled sample is 30/spl times/50 mm/sup 2/ using 1.53 mm glass-epoxy substrate. Basic signal line constructed as 50-ohm characteristic impedance. The soldered thin wire line of 100-micrometer diameter was fabricated at the center of the modeled PCB that simulates the bonding part. S-parameters, i.e. |S/sub 21/| and |S/sub 11/|, characteristic impedance measured by the time domain reflectometry and magnetic near field distribution measured by a shielded loop probe are discussed. The length of the thin wire and shape of the strip line and wire-bonding part have significant influence to the characteristic impedance, transmission property and magnetic distribution properties. These results offer the design ways and guidelines for the PCB and parts designing and wiring including solder mounted element and also wire bonding packaging at high frequency applications.

Deep learning has gained substantial popularity in recent years. Developers mainly rely on libraries and tools to add deep learning capabilities to their software. What kinds of bugs are frequently found in such software? What are the root causes of such bugs? What impacts do such bugs have? Which stages of deep learning pipeline are more bug prone? Are there any antipatterns? Understanding such characteristics of bugs in deep learning software has the potential to foster the development of better deep learning platforms, debugging mechanisms, development practices, and encourage the development of analysis and verification frameworks. Therefore, we study 2716 high-quality posts from Stack Overflow and 500 bug fix commits from Github about five popular deep learning libraries Caffe, Keras, Tensorflow, Theano, and Torch to understand the types of bugs, root causes of bugs, impacts of bugs, bug-prone stage of deep learning pipeline as well as whether there are some common antipatterns found in this buggy software. The key findings of our study include: data bug and logic bug are the most severe bug types in deep learning software appearing more than 48% of the times, major root causes of these bugs are Incorrect Model Parameter (IPS) and Structural Inefficiency (SI) showing up more than 43% of the times.We have also found that the bugs in the usage of deep learning libraries have some common antipatterns.

Purpose – The purpose of this paper is to verify how solder joint properties correlate with soldering profile set-up. These characteristics act against each other. All observed properties may significantly affect the quality and reliability of solder joints. The purpose is also to design recommendations for manufacturers of electronic assemblies. Design/methodology/approach – The samples for experiment were reflowed by using a laboratory reflow oven. A LEXT laser confocal microscope was used for wetting angle and intermetallic compound (IMC) thickness measurement. The ionic contamination was measured by using a contaminometer. Findings – The appropriate choice of soldering profile is very important for the reliability of electronic assemblies. The higher temperatures or longer preheating and soldering times improve the wetting angle. Likewise, there is also the activation of all the fluxes. The result is low contamination with printed circuit boards (PCBs). On the other hand, we must not forget that higher temperatures and longer soldering time also affect the thickness of the IMC. The outer limits recommended by the manufacturer were selected for the soldering profile set-up. Even within these limits, it is possible to achieve an improvement in the wetting angle, an improvement in levels of PCB contamination and an increase in the thickness of the IMC. This paper presents the results achieved for solders Sn42Bi57.6Ag0.4, Sn96.5Ag3Cu0.5 and Sn97Ag3. Originality/value – The gained knowledge on the correlation between IMC thickness, solderability of PCB and PCB contamination caused by different soldering profile set-ups can help to prevent reliability problems because each of the named effects has a significant influence on reliability.

The paper focuses on biodegradable Printed Circuit Boards (PCB) from the aspect of PCB fabrication technology and soldering. Different biodegradable Cellulose Acetate (CA) PCBs were used during the tests (one sided and two sided), and the possible application of pre-preg was also taken into account to improve pad adhesion on the base material. The surfaces of the boards were evaluated in order to obtain information about copper adhesion. FR4 test boards were also investigated as a reference, both for soldering and surface analyses. The soldering profile setup was focused on minimizing high temperatures on the heat-sensitive biopolymer substrates. The soldering profiles were created with a custom vapour phase soldering (VPS) device. The customized solder profile setting is conducted with an adaptive temperature-tracker sample holder. The boards and the solder joints were investigated with non-destructive optical microscopy, X-ray microscopy (deformation and joint analysis), and destructive shear tests. The results are promising for future application of biodegradable PCBs.

The advent of High Density Printed Circuit Board (HD PCB) into electronic assemblies has enabled the evolution of mobile computing devices like smartphones and tablets. System level failure analysis to understand quality and reliability issues of such products is challenging. The presence of blind and buried vias stacked in a multi-layer Printed Circuit Board (PCB) coupled with double sided assemblies without test or probe points for electrical continuity access adds to the complexity. This paper presents one such case study where a detailed failure analysis approach was adopted to identify the root cause of failures. Coupling software and complimentary electrical techniques the problem was isolated to the PCB part of the system assembly. Deep dive material analysis of the fault isolated signals revealed cracks in inner layers of the PCB. The study also highlighted the fact that marginal PCB manufacturing issues could worsen during the thermal exposures associated with motherboard assembly and product usage.

Formulation of the problem. When mounting electronic components on a board during the soldering process, voids inevitably form inside the connection. There are especially many of them in solder joints that have a large area. These voids impair thermal conductivity and generally reduce both the mechanical and electrical reliability of the contact. Therefore, finding ways to reduce the impact of this defect is a fairly urgent task. Target. Consider the effect of solder mask roughness on the distribution of flux around the contact pad, and also identify the dependence of the formation of voids on the configuration and thickness of solder paste application. Results. More active fluxes have been shown to produce fewer voids in terms of average total area covering the pad. Analysis of samples prepared using modified stencils showed a significantly lower proportion of voids than when using a standard stencil. In addition, it has been shown that the choice of solder mask type has a significant impact on the formation of voids in solder joints. The best results were achieved using a thin stencil with a larger aperture when the printed circuit boards were without a solder mask, and the surface has the greatest roughness. However, when modified, thicker, smaller aperture stencils were used, the solder mask had no effect on void formation. Thus, it was found that stencil modification can be recognized as a more preferable and effective way to minimize voids in solder joints. Practical significance. The results obtained can be used to improve the reliability of radio-electronic equipment by selecting optimal soldering technology parameters that affect the reduction of the number of voids in solder joints of components on the board.