Failure Analysis of High Density Printed Circuit Board Assembly Inside Smartphone

Modeling and simulation for a drop-impact analysis of multi-layered printed circuit boards

Printed circuit boards (PCBs) are designed for packing two or more semiconductor chips. On these PCBs, there are various types of faults in the wiring. We must therefore test the PCBs to detect these faults, and it is essential to establish an efficient testing method. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the PCB. The objective is to minimize the completion time for the testing, that is, our aim is to design efficient routes for the two probes; this is a two-probe routing problem. Several previous studies have proposed an approach involving a two-phase method. Although the two-phase method quickly finds a feasible solution, there is no guarantee that the solution is good. Besides, in recent years, PCB technology provides dense assembly capability and increased chip packaging; this implies that the scale of the two-probe routing problem becomes larger and the problem is difficult to be solved. We therefore propose a new approach, where we formulate a two-probe routing problem as a combinatorial optimization problem and then, we solve the combinatorial optimization problem by using genetic algorithm.We expect that our approach is useful for solving the large-scale problems. In computational experiments, we compare the results of our approach with those obtained using the two-phase method, and we show that our approach outperforms the two-phase method.

As the density of interconnects on printed circuit board is increasing tremendously, the use of optical microscope for checking of open trace is running out of steam. While electron microscope has the required resolution, the presence of solder mask on the top surface of the board hinders its direct application. Recently, the method of capacitive coupling voltage contrast (CCVC) method showed the feasibility for such a checking around a small region where open circuit or broken trace is located. In this work, we extend the CCVC method to obtain a contrast map of interconnects on an entire printed circuit board. With the use of simple image processing on the contrast map, both interconnects and the site of open circuit can be observed, making it a useful quality and failure analysis tool for copper traces integrity test. Finite element modeling of the CCVC is also performed, and the results agree qualitative with the experimental results

Planar resistors are discrete thin-film resistive elements formed by standard printed circuit board print-and-etch processing. These resistive elements can be either surface or buried resistors in a multilayer printed circuit board or high density interconnecting substrate. Planar Resistor Technology (PRT) is used to create planar resistors and can be cost effective for high-density electronic applications, reducing the substrate cost as well as the surface mount (SMT) discrete component and assembly cost to achieve an overall cost reduction. Standard cost models compare the fixed PRT area cost to the increasing SMT area cost to determine where increasing component densities make the use of PRT cost effective. Breakeven typically occurs between four and ten resistors per square inch of board area. However, standard cost models do not include other cost adders such as for High Density Interconnect (HDI) technologies that enable higher component and wiring densities. Advanced technology cost models show that substrate and assembly metrics; component density, I/O density and wiring density are the primary determinates of the use of planar resistors for cost optimization. These advanced cost models show that PRT usage is indicated at complexity levels of 100 to 200 I/Os per square inch or interconnect densities of 100 to 160 inches per square inch. Continued use of discrete SMT resistors beyond this range drives up costs as increasing densities force the shift to more expensive interconnect technologies. These technologies shifts are (shown in order of increasing complexity): Single-sided SMT changes to double-sided SMT, Standard multilayer PCBs to sequentially built PCBs with buried vias, Standard multilayer PCBs to HDI substrates with or without microvias. The switch to PRT occurs as an alternative to higher cost sequential build PCBs or HDI substrates needed to interconnect with the SMT resistors. Embedding resistors in existing layers and using conventional PCB technology reduces the cost of the substrate. PCBs using embedded planar resistor technology are less expensive than comparable designs using HDI and SMT chip resistors. The cost advantages of PRT are: Reduced substrate area costs resulting from smaller form factors, Reduced substrate conversion costs (added layers, build-up and/or HDI costs), Reduced discrete SMT component and assembly costs. For cost optimization, the cost of a PCB using buried resistors must be compared to the cost of alternative technologies that enable continued use of SMT components. Planar resistor costs adders are approximately $.25 per square inch per layer. Where the area cost increase of an alternative design exceeds this amount, the use of PRT is indicated.

This paper presents an investigation on field returned open and short failures related to printed circuit board (PCB), including via hole crack, prepreg crack and insufficient circuit etching. After an experimental study with cross section, time domain reflectometry (TDR), and finite element (FE) modelling, it was found that weak plating and corrosion induced via hole crack was a major root cause of interconnect open failures. Such a failure was always mistakenly treated as solder joint open. Except for via hole crack, PCB prepreg crack was another contributor for open failures. The prepreg material for some lot code in production was in poor quality in terms of long-term durability. Dye and pry and cross section investigation showed that for some field returned units, the pad-to-prepreg interface was the weakest adhesion part in the entire solder joint interconnects. Crack propagated across the whole support and hence pad cratering occurred upon overstress. For the circuit short problem, insufficient etching of copper traces and pads was found to be a dominant contributor in harsh environment for a long time. Particularly, corrosion induced dendrite growth brought a high risk of circuit short of insufficiently etched conductors for the fine-pitch lead-free application. In summary, it is important to monitor and control the incoming quality of incoming PCBs so that the the risk of high field return rate and high cost for repair can be minimized.

The micro-hole is a key structure in multilayer printed circuit board (PCB), as it enables the effective transmission of electrical signals. At present, the most common way to machine PCB micro-holes is mechanical drilling using micro-bit. However, in the mechanical drilling of micro-holes, these holes are prone to burring at the hole mouth due to the micro-bit failing to cleanly cut through the first layer of copper foil on the PCB. Hole mouth burr can seriously affect the performance of the PCB, resulting in potential short circuiting or even ruining the PCB. To solve the above problems, this paper proposed to machine the first layer of copper foil on the PCB via micro electro-discharge machining (micro-EDM) to eliminate hole mouth burr. Compared with the mechanical drilling, micro-EDM is a form of non-contact machining, and the high temperature generated from the electric spark discharge can erode the first layer of copper foil, thus fully eliminating hole mouth burr. This paper performed a detailed study of the influence of spindle speed, machining voltage, pulse width, and pulse interval on hole mouth quality. After that, the technological parameters for eliminating hole mouth burr were obtained. Finally, under the effects of 20,000 rpm spindle speed, 26 V machining voltage, 4 μs pulse width, and 8 μs pulse interval, a micro-bit with a diameter of 200 μm was used to perform micro-EDM of the first layer of copper foil. From the machining results, it can be known that the PCB micro-hole was possessed of overall good quality, with good hole wall surface quality and almost no visible hole mouth burr.

In recent years, electronic devices are strongly required to be smaller, lighter, and more powerful. As a result, mounted components have become smaller, more powerful, and denser, and the heat generation density on printed circuit boards (PCBs) has increased. Since rising component temperatures can lead to component failure, efficient heat removal from the generated heat has become an urgent issue. Since general PCBs have low thermal conductivity, when high heat dissipation is required, methods to increase the thermal conductivity of PCBs have been employed by increasing the copper (Cu) content in the PCB or by placing an aluminum (Al) alloy in the inner layer. However, while Cu and Al have high thermal conductivity, they also have high coefficients of thermal expansion (CTE) and young’s modulus, and the CTE of a PCB with increased thermal conductivity using these materials is high. If the thermal expansion difference between the PCB and mounted components is large, reliability against heat cycles cannot be obtained. Therefore, we have focused on copper-molybdenum (CuMo) composite materials with high thermal conductivity, high elastic modulus, and low thermal expansion. We have been utilizing Cu-Mo for the development of our PCBs and fabricated multilayered CuMo composite PCBs; therefore, this report will focus on the results regarding thermal characterization of prototype PCBs.

Edge plating and via stitching connecting ground planes are two common edge treatments to suppress electromagnetic interference (EMI) from multilayer printed circuit boards (PCB). One critical parameter for stitching via is the spacing between vias. At higher frequencies, it is desirable to plate the edges of PCB, and a gap is required in the plating to accommodate the break-off tabs. In this paper, the shielding performance of these two scenarios are studied in both simulation and measurement. By sweeping the parameters of via pitch size and the length of each plated edge, the near-field shielding effectiveness (SE) of these different cases are compared. In general, the edge plating cases have much better shielding performance than the stitching via ones. Since edge plating implements the shielding on PCB walls, it leaves no interference with signals and moreover saves space for dropping GND stitching vias, with a trade-off of 5% more cost. Design guidelines for PCB edge treatments are provided in the end of the paper.

Recently, electric circuits may be become small, and also high-density electrical technologies have advanced. In order to place many elements on the small printed circuit board (PCB), a high-density multi-layered PCB may be used. Many vias are used in such multi-layered PCB to connect lines on each layer. If many vias are placed in narrow area, they make ground slots. If a ground slot exists near a transmission line, the distortion of the signal may be occurred. Then, existence of slots is issue for high-speed circuit designs. In this paper, we analyzed the transmission characteristic of a microstrip line above a ground slot on a PCB using multiconductor transmission-line (MTL) method. First, we measured it for various slot width. And also, we analyzed it using FDTD method. Comparing the results of measurement value and analysis value, a validity of the model of the FDTD method was confirmed. Next, we derived the characteristic impedance of the microstrip line using spectral domain approach (SDA). We calculated the transmission characteristics of the microstrip line above the slot by applying MTL method. And, the analysis values of MTL and FDTD are almost same in the case of small slot up to high frequency.

In this chapter, we report the utilization of spin-valve type giant magnetoresistance (GMR) sensors in non-destructive evaluation (NDE). The NDE application is the inspection of high-density printed circuit boards (PCBs) based on the eddy-current testing (ECT) technique. An ECT probe with a GMR sensor is presented for the inspection of high-density double-layer PCB models. The utilization of a GMR sensor as a magnetic sensor showed that PCB inspection could be performed with high-spatial resolution and sensitivity, over a large frequency range.

A compact common-mode suppression filter is proposed by employing the modified ground structure (MGS) for high speed digital interconnects using differential signals on the multi-layered printed circuit board (PCB). It consists of two folded U-shaped slot resonators and arranged via-holes. It has compact size of 0.073λ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> × 0.225λ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> when the center frequency is 5.2 GHz. A test board is fabricated on four-layered PCB through an optimizing process for verifying effects of the proposed MSG structure. The proposed MGS can suppress the common-mode noise over 10 dB from 4.34 to 6.07 GHz in the frequency domain and over 52% of amplitude in the time domain. Furthermore, the proposed filter still keeps good signal integrity characteristics with regard to the insertion loss of differential-mode signals. It is clear that the proposed filter structure can apply to the multi-layered PCB of commercial mobile devices due to its compact size and have some advantages such as wide bandwidth, gigahertz frequency range, low cost, and PCB embedded design‥

We have analyzed the effect of via in multilayer printed circuit boards (PCBs) on signal integrity and signal delay time of high-speed digital systems. First, the techniques of the circuit modeling of via are discussed. Electrical behaviors of via in interconnects according to its circuit model are characterized through HSPICE simulation. Based on these results, we show that via can behave as being capacitive or inductive according to the characteristic impedance of signal lines, which is different from the fact that via is generally regarded as being only capacitive. The proposed electrical characteristic of via is verified by results of TDR/TDT measurement of through-hole type via in 8-layer PCBs. Second, the methodology of measurement of delay caused by via is proposed. Because it is so difficult to measure the electrical delay of signal passing through one via, we extract the delay caused by single via from measuring the delay when the signal passes through several vias. For an example, we obtained the signal delay time of 12 psec caused by a throughhole type via in 8-layer PCBs. For just two vias, the delay time is about 24 psec and it is about 8% of flight time of 5 cm signal line.

Plated though-hole (PTH) vias are extensively adopted in multilayer printed circuit boards (PCBs). Unused portions of PTH vias become open stubs, which excite the resonance mode and degrade signal integrity (SI). This work investigates how open via stubs in multilayer PCBs affect the time-domain transmission (TDT) waveform and eye diagram. Exactly how time-domain reflection affects the open via stubs on TDT waveform is also studied using the lattice diagram. Additionally, the R and RL terminations of open via stubs are developed to improve SI in previous studies. Moreover, the RC termination of open via stubs is proposed to improve the performance of SI, which is the same as that of the R termination in this work. RC termination is also characterized by its nearly zero DC power consumption. Furthermore, different terminations are compared with respect to how they improve the TDT waveforms and eye diagrams.

Possibilities of improvement in detection and characterisation accuracy concerning internal defects in multi-layered printed circuit boards (PCB) and electronic components by applying the ultrasonic immersion technique have been investigated. The experiments have been carried out on a real PCB with a mounted defective microchip. Defect-free and defective high-voltage semiconductor components have also been investigated. The investigations have been performed using the acoustic microscope produced by Ultrasonic Science Ltd and ultrasonic measurement system developed at the Ultrasound Institute of Kaunas University of Technology. The novel signal processing method based on the adaptive numerical model of ultrasonic wave propagation through a multi-layered electronic component and respective selection of signal components in time and frequency domains have been proposed. Two different signal processing techniques have been used to increase the contrast of defective regions and so improve reliability of ultrasonic inspection.

Gearless and compact motors rotating at speeds above 10,000 rpm are finding many applications nowadays. This study presents the multiphysics modelling and analysis of a multilayer printed circuit board (PCB) stator for high‐speed, low‐power axial flux permanent magnet motor. The possibility of circulating current in the multilayer PCB is studied. The two major effects of eddy currents at high frequencies: skin effect and proximity effect are investigated for the PCB winding. The losses in the PCB stator are estimated, and thermal analysis is performed to ensure reliable operation of the motor. MagNet 3‐D and COMSOL Multiphysics are used, respectively for the finite element analysis and optimisation of the motor; and the simulation results are presented. A prototype of the motor is fabricated and tested to validate the simulation results.