A genetic algorithm for probe testing problem on high-density PCB

The advent of High Density Printed Circuit Board (HD PCB) into electronic assemblies has enabled the evolution of mobile computing devices like smartphones and tablets. System level failure analysis to understand quality and reliability issues of such products is challenging. The presence of blind and buried vias stacked in a multi-layer Printed Circuit Board (PCB) coupled with double sided assemblies without test or probe points for electrical continuity access adds to the complexity. This paper presents one such case study where a detailed failure analysis approach was adopted to identify the root cause of failures. Coupling software and complimentary electrical techniques the problem was isolated to the PCB part of the system assembly. Deep dive material analysis of the fault isolated signals revealed cracks in inner layers of the PCB. The study also highlighted the fact that marginal PCB manufacturing issues could worsen during the thermal exposures associated with motherboard assembly and product usage.

Since the 1960s, interconnection technology has been dominated by implementations of printed circuit board (PCB) technology. However, in response to the ever increasing demand for higher routing densities and improved electrical performance, this technology has been increasingly challenged by multichip module (MCM) technology and in particular the MCM‐L type. MCM‐L technology is a laminate construction and is basically a further development of PCB technology with two or more bare chips and fine line interconnects. Consequently, it is perceived that the current PCB fabricators are ideally positioned to take the initiative with MCM‐L technology. Reviews the current state of PCB industry and MCM‐L technological (process and material) requirements, within the UK, such that a comparison can be made between the two technologies. Planning, training and investment requirements for new technology implementation are then identified and compared with PCB fabricators’ technological, training, planning and investment capabilities. The shortfalls between MCM‐L fabrication requirements and PCB fabricators capability are identified and discussed.

As the density of interconnects on printed circuit board is increasing tremendously, the use of optical microscope for checking of open trace is running out of steam. While electron microscope has the required resolution, the presence of solder mask on the top surface of the board hinders its direct application. Recently, the method of capacitive coupling voltage contrast (CCVC) method showed the feasibility for such a checking around a small region where open circuit or broken trace is located. In this work, we extend the CCVC method to obtain a contrast map of interconnects on an entire printed circuit board. With the use of simple image processing on the contrast map, both interconnects and the site of open circuit can be observed, making it a useful quality and failure analysis tool for copper traces integrity test. Finite element modeling of the CCVC is also performed, and the results agree qualitative with the experimental results

The use of Printed Circuit Board (PCB) technology for device packaging offers new opportunities to solve these challenges. During the past decade embedding of semiconductor chips into PCB structures evolved from a research topic to volume production. The paper will briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia and Europe, mainly for mobile applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to reduce the thickness and size of the module. In order to replace DCB ceramics, a structure of thermal laminate material between Cu layers has been developed and the capability for thermal conduction and electrical insulation has been evaluated. For the assembly of large power IGBTs with sizes of 100 mm² and larger, new silver sintering pastes have been evaluated. They enable a pressure-less sintering at 200 °C, compatible with PCB materials. To handle the high switching current of up to 200 A, suitable copper tracks in the PCB are required. The realization of such thick copper lines with thickness up to 1 mm requires advanced processing, compared to conventional multilayer PCB production. In order to form complex power systems out of modules with embedded chips interconnections by Ag sintering are under development.

High density interconnect printed circuit board technology enables significant board size and layer count reduction. Thinner inner layer dielectric materials, reduced line widths, and closer spaced components inherent in high density board technology require a change in electrical design methodology. Most notably, the thinner dielectric thickness significantly impacts the electrical performance of the circuit board with respect to crosstalk, board capacitance, via inductance, and controlled impedance. Via inductance is significantly reduced as mechanically drilled through hole vias are replaced with microvias. Distributed capacitance will tend to increase because of the thinner dielectric layer and crosstalk between signal traces run on adjacent layers may also increase. Using either FR-4 type epoxy (diel, cnst.=4.0) or higher performance materials (diel, cnst.=2.8) conventional controlled impedance structures such as a stripline, microstrip, and coplanar waveguide are possible to design using current manufacturing capabilities. A 50 /spl Omega/ impedance can be achieved by a microstrip or a coplanar waveguide using either dielectric material. The stripline can only achieve approximately 35 /spl Omega/ with the higher performance material and 25 /spl Omega/ with the FR-4 type epoxy material. A 500 mW radio frequency receiver and transmitter module operating at 467 MHz was successfully fabricated using a three layer build-up high density circuit board. The circuit board construction had one build-up layer fabricated with a liquid epoxy material. The circuit board electrical design incorporated microstrip, stripline, and coplanar waveguide controlled impedance structures. The results of the electrical performance measurements indicated that transmitted power, receiver sensitivity, and frequency specification performance were similar to a six layer board manufactured with conventional technology.

In this chapter, we report the utilization of spin-valve type giant magnetoresistance (GMR) sensors in non-destructive evaluation (NDE). The NDE application is the inspection of high-density printed circuit boards (PCBs) based on the eddy-current testing (ECT) technique. An ECT probe with a GMR sensor is presented for the inspection of high-density double-layer PCB models. The utilization of a GMR sensor as a magnetic sensor showed that PCB inspection could be performed with high-spatial resolution and sensitivity, over a large frequency range.

The conversion to lead-free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity of pad cratering in Printed Circuit Boards (PCBs) [1, 2]. In general, lead-free solder joints are stiffer than tin-lead solder joints, and some lead-free compatible PCB dielectric materials are more brittle than conventional tin-lead compatible PCB materials. These two factors, coupled with the higher peak reflow temperatures for lead-free assembly, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath the BGA corner pads. The likelihood of pad cratering occurring in any given assembly depends on several factors including, but not limited to the BGA package size, construction and surface finish; and the PCB pad size, material and surface finish. Standard assembly level bend and shock tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures. However, with these standard assembly level tests, it is difficult to determine if the failures occur due to a weaker PCB structure or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes. In this study, an easy-to-implement test method is presented in detail, along with calibration and test results comparing a broad spectrum of PCB attributes. Different dielectric materials and pad sizes were evaluated to develop a comparative metric that can be used to rank-order different material/pad size combinations. The results were generated over different pull temperatures and multiple reflows, to study the effect of temperature on dielectric mechanical strength characteristics. Ultimately, these metrics can be used to optimize PCB design, thus mitigating pad cratering potential.

With the miniaturization of the electronic devices, the spacing among the circuit traces on printed circuit boards (PCB) keeps reducing, which increases the risk of insulation failure based on electrochemical migration (ECM), especially for immersion silver (ImAg) plated PCB. Meanwhile, due to the severe air pollution in developing countries, airborne dust can deposit on the PCBs in electronic devices. The soluble salts in the dust can decrease critical humidity and increase the ion concentration in the moisture condensed on the PCB surfaces, so that the failure mechanism based on ECM may be changed and the time to failure (TTF) can be shorten. In this paper, the effect of the soluble salt with various concentrations on the ECM failure on PCB was investigated. The life model of ECM was built up based on the electrochemical reactions on electrodes. Then the ECM of PCB under sodium chloride (NaCl) solution with various concentrations was simulated on Y- pattern PCB by water drop (WD) test method. The failure characteristics of ECM during various stages of migration and under various concentrations of salt solution were analyzed by the morphology and element compositions of dendrite products, as well as real time monitoring of surface insulation resistance (SIR). The TTF of ECM was extracted to fit the life model. Finally, the mechanism and performance of ECM of PCB under salt solution was analyzed. And the application of the life model of the ECM failure of PCB contaminated by soluble salts was discussed.

Virtual test access, offered by Boundary-Scan at In-Circuit Test (ICT), is insufficient for the challenges of next generation's high density Printed Circuit Boards (PCBs). The loss of test access translates to loss of defect coverage. This paper describes a novel use of existing technologies that increases the effectiveness of Boundary-Scan.

We have developed a micro fluxgate magnetic sensor using new printed circuit board (PCB) technology. The fluxgate sensor consisted of five PCB stack layers including one layer of magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core was made of micro patterned amorphous magnetic ribbon with an extremely high DC permeability of ~100,000, and the core had a rectangular ring shape. Four outer layers as an excitation and pickup coils had a planar solenoid structure. The amorphous magnetic core was easily saturated due to the high permeability, low coercive field, and closed magnetic path for the excitation field. The chip size of the fabricated sensing element was 7.3 × 5.7 mm2. Excellent linear response over the range of –100 μT to +100 μT was obtained with sensitivity of 780 V/T at excitation sine wave of 3 Vp-p and 360 kHz. A very low power consumption of ~8 mW was measured. This low power, small size, and high sensitive fluxgate sensor to measure a low magnetic field is very useful for various applications.

A printed circuit board (PCB) is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. A new PCB technology, developed by German company - JUMATECH, called WIRELAID brings possible cost reduction and more design space. By attaching discrete copper wires onto copper foils, WIRELAID technology enables PCB to carry much higher currents. As a result, the combination of power and signal circuits on the same layer, as well as three-dimensional applications can be realized without using expensive thick copper technology or connectors. Wires with different specifications can also be chosen to match different circuit requirements.

Given the increase in digital product waste, demand for recycling of printed circuit boards (PCBs) is increasing. Precious and minor metals are often well concentrated in integrated circuit (IC) chips, especially in PCBs; hence, IC chips are primary targets for recycling. The technology for the non-destructive detachment of IC chips from PCBs is increasing in sophistication; however, the effectiveness of IC chip detachment is currently assessed manually and visually. In the present study, an automated IC chip detachment assessment method was developed, which combines multistep binarization and template matching of X-ray transmission images of crushed PCBs. To validate the method, five types of mechanically crushed PCBs from mobile phones were examined, and the developed method successfully assessed the IC chip detachment rate, with an average error rate of only 2.2% compared to visual assessment.

Engines are prone to various types of faults, and it is crucial to detect and indeed classify them accurately. However, manual fault type detection is time‐consuming and error‐prone. Automated fault type detection promises to reduce inter‐ and intra‐observer variability while ensuring time invariant attention during the observation duration. We have proposed an automated fault‐type detection model based on sound signals to realize these advantageous properties. We have named the detection model prism pattern network (PrismPatNet) to reflect the fact that our design incorporates a novel feature extraction algorithm that was inspired by a 3D prism shape. Our prism pattern model achieves high accuracy with low‐computational complexity. It consists of three main phases: (i) prism pattern inspired multilevel feature generation and maximum pooling operator, (ii) feature ranking and feature selection using neighbourhood component analysis (NCA), and (iii) support vector machine (SVM) based classification. The maximum pooling operator decomposes the sound signal into six levels. The proposed prism pattern algorithm extracts parameter values from both the signal itself and its decompositions. The generated parameter values are merged and fed to the NCA algorithm, which extracts 512 features from that input. The resulting feature vectors are passed on to the SVM classifier, which labels the input as belonging to 1 of 27 classes. We have validated our model with a newly collected dataset containing the sound of (1) a normal engine and (2) 26 different types of engine faults. Our model reached an accuracy of 99.19% and 98.75% using 80:20 hold‐out validation and 10‐fold cross‐validation, respectively. Compared with previous studies, our model achieved the highest overall classification accuracy even though our model was tasked with identifying significantly more fault classes. This performance indicates that our PrismPatNet model is ready to be installed in real‐world applications.

Electromagnetic (EM) radiation from a feed cable attached to a printed circuit board (PCB), which is commonly encountered electromagnetic interference (EMI) problem at high-speed electronic PCB designs, is investigated by experimental and finite-difference time-domain (FDTD) modeling. In this paper, we propose and demonstrate a guard-band structure as a method for suppressing the EM radiation from a PCB with a feed cable. A signal trace is located between two ground traces (guard-band: GB). Four different cross-sectional PCB structures, which are commonly used in microwave integrated circuits as typical structures, are used to compare the guard-band structure. Frequency response of common-mode (CM) current, electric field near a PCB, and far electric field (radiated emission) are investigated as characteristics of the EMI. Results show that the shield structure is effective in suppressing the CM current at lower frequency. However, structures in which a conductive plate exists near the signal trace yield resonances with high level peak on CM current, near and far-field. On the other hand, the guard-band structure is more effective than other structures in suppressing the EM radiation in the considered frequency range. Therefore the guard-band will be effective for high-density PCB packaging with high-speed traces.

Testing of electronic systems using conventional testing methods has become more difficult and costly as these systems have become more complex and compact. Conventional testing methods and systems often require lengthy analysis to define testing strategies. These test systems may require lengthy test periods, complex stimulus and measurement instrumentation as well as complicated fixturing. The results are often ambiguous and require further interpretation. This paper presents an exploration of a "non-intrusive" test method based on interpreting changes in the magnetic field close to a Printed Circuit Board (PCB). Currents moving between devices on the PCB produce these magnetic fields. Changes of the PCB operational status due to faults cause changes in the associated magnetic field pattern that can be interpreted by Artificial Neural Networks (ANNs) for fault identification. An apparatus to collect magnetic field measurements is described along with some problems of collecting data. Typical magnetic field patterns for "known-good" and faulted PCBs are presented. Possible extensions of the method are discussed. This paper resulted from internally funded work at Southwest Research Institute (SwRI) concerning non-intrusive diagnostic techniques.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>