Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application

The advent of High Density Printed Circuit Board (HD PCB) into electronic assemblies has enabled the evolution of mobile computing devices like smartphones and tablets. System level failure analysis to understand quality and reliability issues of such products is challenging. The presence of blind and buried vias stacked in a multi-layer Printed Circuit Board (PCB) coupled with double sided assemblies without test or probe points for electrical continuity access adds to the complexity. This paper presents one such case study where a detailed failure analysis approach was adopted to identify the root cause of failures. Coupling software and complimentary electrical techniques the problem was isolated to the PCB part of the system assembly. Deep dive material analysis of the fault isolated signals revealed cracks in inner layers of the PCB. The study also highlighted the fact that marginal PCB manufacturing issues could worsen during the thermal exposures associated with motherboard assembly and product usage.

Printed circuit boards (PCBs) are designed for packing two or more semiconductor chips. On these PCBs, there are various types of faults in the wiring. We must therefore test the PCBs to detect these faults, and it is essential to establish an efficient testing method. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the PCB. The objective is to minimize the completion time for the testing, that is, our aim is to design efficient routes for the two probes; this is a two-probe routing problem. Several previous studies have proposed an approach involving a two-phase method. Although the two-phase method quickly finds a feasible solution, there is no guarantee that the solution is good. Besides, in recent years, PCB technology provides dense assembly capability and increased chip packaging; this implies that the scale of the two-probe routing problem becomes larger and the problem is difficult to be solved. We therefore propose a new approach, where we formulate a two-probe routing problem as a combinatorial optimization problem and then, we solve the combinatorial optimization problem by using genetic algorithm.We expect that our approach is useful for solving the large-scale problems. In computational experiments, we compare the results of our approach with those obtained using the two-phase method, and we show that our approach outperforms the two-phase method.

High density interconnect printed circuit board technology enables significant board size and layer count reduction. Thinner inner layer dielectric materials, reduced line widths, and closer spaced components inherent in high density board technology require a change in electrical design methodology. Most notably, the thinner dielectric thickness significantly impacts the electrical performance of the circuit board with respect to crosstalk, board capacitance, via inductance, and controlled impedance. Via inductance is significantly reduced as mechanically drilled through hole vias are replaced with microvias. Distributed capacitance will tend to increase because of the thinner dielectric layer and crosstalk between signal traces run on adjacent layers may also increase. Using either FR-4 type epoxy (diel, cnst.=4.0) or higher performance materials (diel, cnst.=2.8) conventional controlled impedance structures such as a stripline, microstrip, and coplanar waveguide are possible to design using current manufacturing capabilities. A 50 /spl Omega/ impedance can be achieved by a microstrip or a coplanar waveguide using either dielectric material. The stripline can only achieve approximately 35 /spl Omega/ with the higher performance material and 25 /spl Omega/ with the FR-4 type epoxy material. A 500 mW radio frequency receiver and transmitter module operating at 467 MHz was successfully fabricated using a three layer build-up high density circuit board. The circuit board construction had one build-up layer fabricated with a liquid epoxy material. The circuit board electrical design incorporated microstrip, stripline, and coplanar waveguide controlled impedance structures. The results of the electrical performance measurements indicated that transmitted power, receiver sensitivity, and frequency specification performance were similar to a six layer board manufactured with conventional technology.

As the density of interconnects on printed circuit board is increasing tremendously, the use of optical microscope for checking of open trace is running out of steam. While electron microscope has the required resolution, the presence of solder mask on the top surface of the board hinders its direct application. Recently, the method of capacitive coupling voltage contrast (CCVC) method showed the feasibility for such a checking around a small region where open circuit or broken trace is located. In this work, we extend the CCVC method to obtain a contrast map of interconnects on an entire printed circuit board. With the use of simple image processing on the contrast map, both interconnects and the site of open circuit can be observed, making it a useful quality and failure analysis tool for copper traces integrity test. Finite element modeling of the CCVC is also performed, and the results agree qualitative with the experimental results

In this chapter, we report the utilization of spin-valve type giant magnetoresistance (GMR) sensors in non-destructive evaluation (NDE). The NDE application is the inspection of high-density printed circuit boards (PCBs) based on the eddy-current testing (ECT) technique. An ECT probe with a GMR sensor is presented for the inspection of high-density double-layer PCB models. The utilization of a GMR sensor as a magnetic sensor showed that PCB inspection could be performed with high-spatial resolution and sensitivity, over a large frequency range.

The popularity of Ball Grid Array (BGA) has been gaining momentum in the past few years. From a board assemblers' perspective, BGA offers a wide process window and low process defect rate. In the early years, the reliability of the BGA solder joints was a concern because the BGA joints are non-compliant in comparison to the joints of gull-wing QFPs. Since then many finite element analysis (FEA) and reliability studies have been published demonstrating that BGA solder joints can have adequate reliability against the shear stress caused by the mismatch of coefficient of thermal expansion (CTE). Another mode of BGA joint failure, which has not been discussed as much, is the flexure-induced failure. In a typical electronics manufacturing environment, the printed circuit boards are handled many times after surface mount and wave soldering. Hand soldering, rework, in-circuit test, functional test, and final assembly are just some of the processes before the product is eventually shipped. Most of these processes can cause bending or warping of the printed circuit assembly (PCA), On a PCA, the areas under and adjacent to the BGA components are relatively rigid compared to the rest of the board. Hence, with the same amount of board flexing, the BGA solder joints become more susceptible to fracture compared to other surface mount devices. This study employed thermal cycling, dye-penetrant test, cross-sectioning, highly accelerated life test (HALT, thermal/vibration test), highly accelerated stress auditing (HASA, thermal/vibration test), “sticky probe” with in-circuit test (ICT) fixture and strain gage measurement to investigate the failure mechanism, and to determine the effects associated with board flexure. It was discovered that excessive flexing of PCA does cause catastrophic BGA solder joint cracking. Localized board flexure during in-circuit test was found to be very high and detrimental. BGA solder joints can crack during the in-circuit test and result in opens or intermittent failures. The ICT fixture should be carefully designed and manufactured to minimize local board warp around the BGA components. A FEA tool to analyze the localized strain on the PCA can be very helpful in ICT fixture design.

In-Circuit-Test (ICT) is an inevitable process for sustaining the quality of Printed Circuit Boards (PCBs) in the assembly and fabrication process. Applying automation to reduce labor and preventing errors in ICT has been studying by academics and industries for decades. Here we demonstrate a robot centric ICT testing system that integrates the peripheral equipment, also including the shop flow control system (SPCS). The graphic programming software – LabVIEW exploits to integrate robot arm, in-circuit test machine, PLC, HMI, and barcode reader. Communication among the facilities and error handling are the main challenges in the automated ICT system development. Heterogeneous communication protocols and third-party devices with unique syntax have caused some programming difficulties. The challenge of error handling is that it might be on hardware, software, or communication. Moreover, these errors may have occurred at 5-6 different facilities with chain effects. The robot arm dominates the main control sequence from the test start to finish. As a result, a steady automated ICT test system with real-time status monitoring has presented. That assists field personnel in eliminating problems quickly and promotes overall production line operation efficiency.

FC-BGA packages that have been used for high performance servers and communication systems, are exposed to mechanical stress during several tests such as In-Circuit Test (ICT), after mounted on a printed circuit board (PCB). Because fast bending load acts on PCB during ICT, high stress is generated in the solder joints of FC-BGA. Therefore, it is important to clarify the solder joint strength under this fast bending condition in order to improve reliability of solder joints. In this paper, fast four-point bending tests of BGA packages mounted on test substrates were performed, in order to develop the evaluation method of BGA solder joint strength corresponding to the mechanical load. Effect of hold time after package mount, loading rate and land plating conditions for solder joints were investigated by the fast four-point bending tests. It was found that a crack propagates in the intermetallic layer of Ni/Sn, and a lot of "Kirkendall Void" was observed in this layer. Furthermore, it was also found that the strength of Pb free solder is higher than that of Sn-Pb eutectic solder.

The components and the solder joints that are made during assembly to hold components to their printed circuit board can suffer from defects and therefore need to be tested. Many research papers on board-Assembly testing focus on boundary scan test, processor-controlled test, or other powered digital testing techniques that mostly ignore the indispensable passive circuits and that can incur damage that could have been avoided by executing a non-powered test first. In-circuit testing is a non-powered test method that applies stimuli and measures responses using probe needles. However, often used self-learning solutions for designing these tests need a known-good-board, entailing significant disadvantages. In this paper, a software tool is described that automatically generates in-circuit tests based on the product design files, without requiring probe access on every net. Furthermore, the tool indicates where on the board fault coverage is not maximal, and hence where extra probe access will improve the test quality.

State of the art manufacturing of microelectronics involves the electrodeposition of copper for fabricating on-chip interconnects, through-silicon-vias for chip stacking, and high density printed circuit boards. This lecture will present a selection of highlights related to superconformal electrodeposition of Cu ranging from its history to its impact on processing of microelectronic circuitry and, more generally, the understanding of additive effects in electrodeposition. The story begins in the mid-20th century with the formal discovery of the effectiveness of plating additives in yielding smooth surfaces i.e. brighteners and levelers, before pivoting to the IBM paradigm changing introduction of complex 3-D Damascene Cu superfilling for on-chip interconnects in 1997. The role of electroanalytical, metallurgical, and surface science measurements along with insights, and modeling to develop a mechanistic understanding of morphological and microstructural evolution during trench and via filling will be detailed. The lessons learned and their extension to other chemical systems and applications will be discussed along with the challenges that lie ahead.

This paper describes the effort to miniaturize common mode filters based on electromagnetic bandgap structures. It describes the proposed approach by means of a systematic analysis of different configurations. The typical 3-patch configuration proposed in the past is modified removing the central patch and the bridge dimensions are tuned for keeping the same target frequency. The analysis of the crosstalk is carried out for the relevant configurations in order to assess the possible implementation of these structures in high density printed circuit boards. The simulation results are discussed and compared to identify the best miniaturized geometry for a practical implementation.

High Density Printed Circuit Board Design and General-Purpose Digital Circuit Extended Board Development

特集 薄形・多層配線板による最小・最薄・最軽量機器実装技術の動向 ８ｍｍビデオ一体型カメラの実装技術

A new method for fabricating high density printed circuit boards has been investigated. The procedure used for photoselective metal deposition on the substrate consists of five steps: adhesion treatment, sensitization, nucleation, fog inhibition and electroless metal deposition. An adhesive coated substrate was sensitized by introducing an aqueous solution containig anthraquinone sulfonic acid sodium salts, reducible noble metal salts and alcohol. The sensitized substrate was then exposed through a mask to a u.v. light. The noble metal nuclei produced by exposure were developed by electroless copper deposition after rinsing with aqueous solutions containing complex agents. Electrically‐conductive patterns thus obtained can be further intensified by second electroless plate making.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.