Electrical design and simulation of high density printed circuit boards

Advances in the capability of IC packaging, component technologies, and printed circuit board manufacturing has given wireless product designers the ability to develop highly functional devices in small form factors. Technologies such as 2D and 3D chip scale packages (CSP), 0201 microcomponents, high density circuit boards, and embedded/integrated substrates have enabled portable wireless products with digital pad densities greater than 600 pads/in/sup 2/ when only two years ago pad densities were <350 pads/in/sup 2/. This paper discusses the methodology developed and tools deployed to select the appropriate component technology and enable high-density physical designs. It provides an in-depth look at the system-level approach used to enable high-density designs in 3G and iDEN/spl reg/ wireless phones and public safety radios which integrate high pin count 0.5 mm micro-BGAs, multi-layer high density interconnect printed circuit boards, and 0201 chip components.

The advent of High Density Printed Circuit Board (HD PCB) into electronic assemblies has enabled the evolution of mobile computing devices like smartphones and tablets. System level failure analysis to understand quality and reliability issues of such products is challenging. The presence of blind and buried vias stacked in a multi-layer Printed Circuit Board (PCB) coupled with double sided assemblies without test or probe points for electrical continuity access adds to the complexity. This paper presents one such case study where a detailed failure analysis approach was adopted to identify the root cause of failures. Coupling software and complimentary electrical techniques the problem was isolated to the PCB part of the system assembly. Deep dive material analysis of the fault isolated signals revealed cracks in inner layers of the PCB. The study also highlighted the fact that marginal PCB manufacturing issues could worsen during the thermal exposures associated with motherboard assembly and product usage.

Printed circuit boards (PCBs) are designed for packing two or more semiconductor chips. On these PCBs, there are various types of faults in the wiring. We must therefore test the PCBs to detect these faults, and it is essential to establish an efficient testing method. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the PCB. The objective is to minimize the completion time for the testing, that is, our aim is to design efficient routes for the two probes; this is a two-probe routing problem. Several previous studies have proposed an approach involving a two-phase method. Although the two-phase method quickly finds a feasible solution, there is no guarantee that the solution is good. Besides, in recent years, PCB technology provides dense assembly capability and increased chip packaging; this implies that the scale of the two-probe routing problem becomes larger and the problem is difficult to be solved. We therefore propose a new approach, where we formulate a two-probe routing problem as a combinatorial optimization problem and then, we solve the combinatorial optimization problem by using genetic algorithm.We expect that our approach is useful for solving the large-scale problems. In computational experiments, we compare the results of our approach with those obtained using the two-phase method, and we show that our approach outperforms the two-phase method.

As the density of interconnects on printed circuit board is increasing tremendously, the use of optical microscope for checking of open trace is running out of steam. While electron microscope has the required resolution, the presence of solder mask on the top surface of the board hinders its direct application. Recently, the method of capacitive coupling voltage contrast (CCVC) method showed the feasibility for such a checking around a small region where open circuit or broken trace is located. In this work, we extend the CCVC method to obtain a contrast map of interconnects on an entire printed circuit board. With the use of simple image processing on the contrast map, both interconnects and the site of open circuit can be observed, making it a useful quality and failure analysis tool for copper traces integrity test. Finite element modeling of the CCVC is also performed, and the results agree qualitative with the experimental results

Virtual test access, offered by Boundary-Scan at In-Circuit Test (ICT), is insufficient for the challenges of next generation's high density Printed Circuit Boards (PCBs). The loss of test access translates to loss of defect coverage. This paper describes a novel use of existing technologies that increases the effectiveness of Boundary-Scan.

In this chapter, we report the utilization of spin-valve type giant magnetoresistance (GMR) sensors in non-destructive evaluation (NDE). The NDE application is the inspection of high-density printed circuit boards (PCBs) based on the eddy-current testing (ECT) technique. An ECT probe with a GMR sensor is presented for the inspection of high-density double-layer PCB models. The utilization of a GMR sensor as a magnetic sensor showed that PCB inspection could be performed with high-spatial resolution and sensitivity, over a large frequency range.

The materials used in the field of printed circuit boards are becoming increasingly complex as they are common to make use of numerous combination of metallic and composite plies. The potential for utilization of circuit boards is generally verified through the numerical simulation, especially for the multilayer printed circuit boards with high electronic density. This paper provides a numerical model intended to describe numerically the behavior of multilayer multimaterial circuit boards. Two parts are considered in the developed model: one is elastic-plastic damaging model that is presented to describe the metallic ply in the multilayer circuit boards; another is degenerated bi-phase model that is presented to describe composite ply. With the combination of equivalent laminate (EQLAM) method, the degenerated bi-phase successfully models the woven glass-fiber/epoxy-resin composite ply. These two plies are the basic components of multilayer circuit boards. Meanwhile, with the verification of static tests and dynamic tests, the reliability of presented model is confirmed.

We have developed a new powder magnetic core, named the high-density magnetic composite (HDMC), with high density, high magnetic flux density, and high strength. However, the HDMC, which was fabricated from iron powder coated with a phosphate amorphous insulator, has large eddy-current loss under high frequency because the resistivity was small (<10 /spl mu//spl Omega//spl middot/m). To solve the deficiency, a new type of phosphate amorphous insulator was developed. The phosphate amorphous insulator with Sr/sup 2+/ or Y/sup 3+/ was found to have high resistivity above 50 /spl mu//spl Omega//spl middot/m in keeping the high magnetic flux density and strength of the HDMC. The HDMC, whose starting material was iron powder coated with a strontium phosphate amorphous insulator, compacted at 1176 MPa with heat treatment at 673 K and had properties as follows: d=7.70 Mg/m/sup 3/, /spl mu//sub m/=610,B/sub 5k/=1.51 T B/sub 10k/=1.71 T, /sub b/H/sub c/=300 A/m, resistivity=100 /spl mu//spl Omega//spl middot/m, TRS=180 MP, iron loss (B/sub max/=1 T,f=400 Hz)=400 kW/m/sup 3/.

The conventional MMIC coplanar line covers an impedance range from about 30-80 /spl Omega/. Values outside this range cannot be fabricated reliably or cause excessive losses, For several applications, however, it is desirable to use high-impedance lines (e,g., for reduced-size couplers and nonlinear transmission lines). This letter reports results from experiment and electromagnetic simulation for a coplanar waveguide (CPW) structure with an elevated center conductor realized by an air-bridge technique. We achieve wave impedances of about 100 /spl Omega/ at a lower attenuation level as conventional 50-/spl Omega/ CPW's of comparable size.

"Electronic manufacturing is currently one of the fastest growing industrial areas. This is due to the rapid advances in the computer and telecommunications sectors. Due to these advances, new surface mount devices have been developed to achieve greater miniaturisation at lower costs. As a result, a new surface mount technology has been developed to mount these devices onto printed circuit boards. However, problems exist with aspects of this process, principally open solder joints which result from circuit board warpage. The aim of this thesis is to undertake a) both an experimental and theoretical investigation of the reflow solder process and b) to develop thermal and structural models to analyse circuit board warpage. This research should aid manufacturing engineers in understanding the influence of the solder reflow process parameters on board warpage. Extensive experimental testing of the circuit board materials during the process is also presented. The thermal model detailed in this thesis simulates a) forced convective heat transfer through air impingement to the boards and b) the three dimensional temperature distribution within a composite laminate. The thermal model predicts the temperature distribution within a populated laminated composite circuit board to within 3% when compared to experimental data. The experimental results show that the convective heat transfer coefficient is primarily dependant on Reynolds number, and also the orifice to plate distance and orifice diameter. It was found that at high Reynolds number, the heat transfer coefficient increases significantly at low orifice to board distance. This heat transfer rate has to be balanced against the maximum speed of the air to prevent the components been blown off the boards. The 5mm diameter orifice provides the optimum balance between air speed and heat transfer rate. The structural model simulates the influence of a) board support, b) reflow temperature profile, c) components on the board and d) board layup on circuit board deformation. The experimental appraisal and model predictions show that the warpage of the printed circuit boards is dependant on a) support of the board during the process, b) symmetry of the board layup, c) coefficients of thermal expansion of the board materials, d) temperature distribution in the boards i.e. symmetric or nonsymmetric about board centre and e) temperature applied to the board. This research proves that if adequate support is applied to the boards during the reflow soldering process then, the warpage of the printed circuit boards may be kept within acceptable margins. Board warpage exists in current printed circuit boards because a) the boards cannot be manufactured truly symmetric in layup and b) Non-uniform temperature distributions are present in the board during the solder reflow process which leads to non-uniform expansion of the constituent laminate layers due to their varying coefficients of thermal expansion."

This study analyzes laser processing of glass-based printed circuit boards which have the capability to replace conventional substrate materials when electronics are required to operate at elevated temperatures. There is significant potential for glass-based circuit boards within the field of aerospace and electric mobility. The new circuit board concept consists of thin copper-coated borosilicate glass with thicknesses ranging from 150 µm to 500 µm. Conventional mechanical processing of this new circuit boards induces stress on the thin glass which can lead to damage of the substrate. Therefore, laser processing with a picosecond laser source is suggested as a tool within the production process of the new circuit boards. Two necessary processes are investigated using a pulsed picosecond laser with a pulse duration of 7 ps at a wavelength of 515 nm. Precise drill-holes for vertical connections of multilayer boards were produced where chipping at the cutting edge must be avoided. Selective ablation of the copper coating was performed to generate the electrical circuits. The results show that a well-defined ablation process is crucial to achieve adequate electrical isolation without damaging the glass substrate. The study also underlines the huge potential of laser processing with picosecond laser sources, which have proven to be a versatile instrument to drill thin glass and generate electrical circuits by selective ablation.This study analyzes laser processing of glass-based printed circuit boards which have the capability to replace conventional substrate materials when electronics are required to operate at elevated temperatures. There is significant potential for glass-based circuit boards within the field of aerospace and electric mobility. The new circuit board concept consists of thin copper-coated borosilicate glass with thicknesses ranging from 150 µm to 500 µm. Conventional mechanical processing of this new circuit boards induces stress on the thin glass which can lead to damage of the substrate. Therefore, laser processing with a picosecond laser source is suggested as a tool within the production process of the new circuit boards. Two necessary processes are investigated using a pulsed picosecond laser with a pulse duration of 7 ps at a wavelength of 515 nm. Precise drill-holes for vertical connections of multilayer boards were produced where chipping at the cutting edge must be avoided. Selective ablation of the ...

We investigated the propagation losses and the characteristic impedances Z/sub L/ of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 /spl mu/m thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan /spl delta/). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 /spl mu/m thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z/sub L/ of 50 /spl Omega/ was also studied in detail.

The blind via holes formation by laser drilling is one of the key technologies for demanding high density interconnect printed circuit boards. In this paper , the drilling conditions of drilling the blind via holes and the quality of the drilled holes are examined using a CO2 laser source against the FR4 board without copper foil.We chose laser energy,pulse shot,pulse width and diameter of beam as the experimental parameter . The results showed that laser energy and beam diameter played a more important role on changing the blind vias’ diameter than pulse shot and pulse width .While the pulse shot and pulse width take more important role in changing the depth of vias.

An innovative approach is described for diagnosing faults in printed circuit boards (PCB) and PCB components through the detection, analysis, and localization of electrical field changes that occur within and around the PCB. This method utilizes electromagnetic emissions (EME) originating from the PCB to determine circuit health. EME from rapidly changing voltages and currents within high-speed logic and other circuits have traditionally been seen as a problematic source of interference that must be eliminated to as great an extent as possible. However, changes within these emissions can be a highly significant indicator that a failure has occurred within a PCB component as well as within adjacent circuit card paths of the board itself. Further, the hardware and software requirements needed to capture and analyze these emissions are relatively simple in comparison to todaypsilas highly complex automatic test equipment. This unique approach involves analyzing electromagnetic emission signatures through automated means, and ascribing failures to the circuit board as a whole, as well as to the individual circuit board components.

Heterodyne focal plane arrays used in the terahertz (THz) regime currently require a discrete set of rigid coaxial cables for the transmission of individual intermediate frequency (IF) signals. Consequently, the size of an array is limited to ~10s of pixels due to limited physical space and the complexity of assembly. In order to achieve an array with ~1000 pixels or greater, new interconnections must be developed capable of carrying multiple IF signals on a single carrier which is flexible, robust to noise, and terminated with a high density RF connector. As an intermediate step to the development of a ~1000 pixel heterodyne focal plane array, the Kilopixel Array Pathfinder Project (KAPPa) has developed a 16 channel IF flex circuit. Initially, design simulations were performed to evaluate various means of high-frequency (1~10 GHz) signal transmission, including microstrip, stripline and coplanar waveguides. The method allowing for the closest signal spacing and greatest resistance to radio frequency interference (RFI) was determined to be stripline. Designs were considered where stripline transitioned to microstrip in order to terminate the signal. As microstrip transmission lines are sensitive to RFI, a design featuring just stripline was evaluated. In both the stripline-to-microstrip and stripline-only designs, a three-layer copper-coated polyimide substrate was used. Signal transitions were accomplished by a signal carrying “hot” via passing through a series of three conductive pads, similar to work by Leib et al. (2010). The transition design essentially mimics a coaxial line, where the radial distance between the pads and the ground plane is optimized in order to achieve desired impedances. In simulation, 50 Ohm impedances were achieved throughout, with crosstalk and return loss limited to -30dB. Terminations are made via an array of Corning Gilbert G3PO blind mate connectors, which are small enough to match the 6mm pixel pitch of the KAPPa focal plane unit. In addition, circuits with SMA terminations were designed to enable straightforward testing with a vector network analyzer (VNA). Initial designs use ½ oz. (18 microns thickness) copper conductors. In the KAPPa application, the copper conductor is still suitable for cryogenic applications because of the very small cross section presented by the copper conductor. The stripline design allows the interconnect to be clamped securely for heat sinking with a copper clamp at 10K and 60K. Heat load to the 4K stage is limited to 10 mW if the circuit is heat sunk at 10K 150mm from the 4K focal plane. Future designs could be implemented with phosphor bronze as the conductor to further limit heat load at the expense of added loss.